Click above to get retro games delivered to your door ever month!

SHLD            Double Precision Shift Left          Flags: O D I T S Z A P C
                                                            ? - - - * * ? * *
SHLD operand1,operand2,count                         CPU: 386+

        Logic   operand1 . high (SHL (operand1:operand2),count)

    SHLD concatenates the two 16- or 32-bit operands into a 32-bit or
    64-bit value (operand2 is the low-order), shifts the value left
    by count bit positions, and returns the high-order of the result
    to operand1. Operand2 is not changed by SHLD.

    The count operand is provided by either an immediate 8-bit value
    or the contents of the CL register; only the lower 5 bits are
    used, limiting the count value to 31.

    The carry flag (CF) is set to the value of the last bit shifted
    out. The overflow flag (OF) is undefined.


        Example:
                ; Shift 64 bits left by 8
                dataseg
                val1  dd 98765432h
                val2  dd 001EDCBAh
                codeseg
                p386n
                mov   cl, 8             ; CL = shift count
                mov   eax, [val1]       ; Load low dword
                shld  [val2], eax, cl   ; Shift into high dword
                shl   [val1], cl        ; Adjust low dword
                ; val1 = 76543200h
                ; val2 = 1EDCBA98h


    Opcode      Format
    0F A4       SHLD r/m16,r16,imm8
    0F A4       SHLD r/m32,r32,imm8
    0F A5       SHLD r/m16,r16,CL
    0F A5       SHLD r/m32,r32,CL


    Length and timing
    Operands        Bytes                      386     486     Pentium
    reg, reg, imm    4                          3       2       4   NP
    mem, reg, imm   4+d(0-2)                    7       3       4   NP
    reg, reg, cl     4                          3       3       4   NP
    mem, reg, cl    4+d(0-2)                    7       4       5   NP