Click above to get retro games delivered to your door ever month!

SHR             Shift Logical Right                  Flags: O D I T S Z A P C
                                                            * - - - * * ? * *
SHR destination,count

                         +---------------+   +----+
                    0 --.|  destination  |--.| CF |
                         +---------------+   +----+

    SHR shifts the bits of the destination operand downward (toward
    the least significant bit) by the number of bit positions
    specified in the second operand (count). As bits are transferred
    out of the right (low-order) end of the destination, zero bits are
    shifted into the left (high-order) end. The carry flag (CF) is set
    equal to the last bit shifted out of the right end.

    The shift is repeated the number of times indicated by the second
    operand, which is either an immediate 8-bit value (max. 1 on the
    8086 processor) or the contents of the CL register. To reduce the
    maximum execution time, the 80186+ uses only the lower 5 bits of
    the count, limiting the count value to 31; the 8086 uses all 8
    bits of count.

    If the count operand is not an immediate 1, the overflow flag (OF)
    is undefined; otherwise SHR sets OF equal to the high-order bit of
    the original operand (i.e. 1 if the sign bit was changed).


    SHR divides an unsigned integer by a power-of-two.

        Example:        shr   dx, 1     ; Shift right 1 bit
                        rcr   ax, 1     ; Propagate carry


    Opcode      Format
    C0 /5 ib    SHR  r/m8,imm8
    C1 /5 ib    SHR  r/m16,imm8
    C1 /5 ib    SHR  r/m32,imm8
    D0 /5       SHR  r/m8,1
    D1 /5       SHR  r/m16,1
    D1 /5       SHR  r/m32,1
    D2 /5       SHR  r/m8,CL
    D3 /5       SHR  r/m16,CL
    D3 /5       SHR  r/m32,CL


    Length and timing
    Same as SAR