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X-Hacker.org- iAPx86 - <b>shrd double precision shift right flags: o d i t s z a p c</b>
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SHRD Double Precision Shift Right Flags: O D I T S Z A P C
? - - - * * ? * *
SHRD operand1,operand2,count CPU: 386+
Logic operand1 . low (SHR (operand2:operand1),count)
SHRD concatenates the two 16- or 32-bit operands into a 32-bit or
64-bit value (operand2 is the high-order), shifts the value right
by count bit positions, and returns the low-order of the result
to operand1. Operand2 is not changed by SHRD.
The count operand is provided by either an immediate 8-bit value
or the contents of the CL register; only the lower 5 bits are
used, limiting the count value to 31.
The carry flag (CF) is set to the value of the last bit shifted
out. The overflow flag (OF) is undefined.
Example:
; Shift 64 bits right by 8
p386n ; edx eax
; ; 0FEDCBA98h 76543210h
shrd eax, edx, 8 ; 0FEDCBA98h 98765432h
shr edx, 8 ; 000FEDCBAh 98765432h
Opcode Format
0F AC SHRD r/m16,r16,imm8
0F AC SHRD r/m32,r32,imm8
0F AD SHRD r/m16,r16,CL
0F AD SHRD r/m32,r32,CL
Length and timing
Operands Bytes 386 486 Pentium
reg, reg, imm 4 3 2 4 NP
mem, reg, imm 4+d(0-2) 7 3 4 NP
reg, reg, cl 4 3 3 4 NP
mem, reg, cl 4+d(0-2) 7 4 5 NP
See Also: SHR ROR RCR SHL SHLD Flags
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