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ROL             Rotate Left                          Flags: O D I T S Z A P C
                                                            * - - - - - - - *
ROL destination,count

                      +----+    +---------------+
                      | CF |.---|  destination  |.-+
                      +----+  | +---------------+  |
                              +-.------------------+

    ROL shifts the bits of the destination to the left by the number
    of bit positions specified in the count operand. As bits are
    transferred out the left (high-order) end of the destination, they
    re-enter on the right (low-order) end. The carry flag (CF) is
    updated to match the last bit shifted out of the left end.

    The shift is repeated the number of times indicated by the second
    operand, which is either an immediate 8-bit value (max. 1 on the
    8086 processor) or the contents of the CL register. To reduce the
    maximum execution time, the 80186+ uses only the lower 5 bits of
    the count, limiting the count value to 31; the 8086 uses all 8
    bits of count.

    If the count operand is not an immediate 1, the overflow flag (OF)
    is undefined; otherwise ROL sets OF to 0 if destination's sign bit
    was not changed by the operation, to 1 if the sign bit was changed.


    Opcode      Format
    C0 /0 ib    ROL  r/m8,imm8
    C1 /0 ib    ROL  r/m16,imm8
    C1 /0 ib    ROL  r/m32,imm8
    D0 /0       ROL  r/m8,1
    D1 /0       ROL  r/m16,1
    D1 /0       ROL  r/m32,1
    D2 /0       ROL  r/m8,CL
    D3 /0       ROL  r/m16,CL
    D3 /0       ROL  r/m32,CL


    Length and timing
    Operands    Bytes   8088    186     286     386     486     Pentium
    reg, 1       2       2       2       2       3       3       1   PU
    mem, 1    2+d(0,2)  23+EA   15       7       7       4       3   PU
    reg, cl      2       8+4n    5+n    5+n      3       3       4   NP
    mem, cl   2+d(0,2) 28+EA+4n 17+n    8+n      7       4       4   NP
    reg, imm     3       -       5+n    5+n      3       2       1   PU
    mem, imm  3+d(0,2)   -      17+n    8+n      7       4       3   PU*

       * = not pairable if there is a displacement and immediate