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      Two status registers, ST0 and ST1, contain the status of various
      conditions and modes. The status registers can be stored in data
      memory and loaded from data memory, thus allowing the status of the
      machine to be saved and restored for interrupts and subroutines. All
      status bits are written to and read from using LST/LST1 and SST/SST1
      instructions, respectively (with the exception of INTM, which cannot
      be loaded via a LST instruction).

               15 14 13 12  11 10    9  8  7  6  5  4  3  2  1  0
              +---------------------------------------------------+
          ST0 |   ARP  |OV|OVM| 1|INTM|            DP             |
              +---------------------------------------------------+

                15 14 13  12 11  10  9  8  7  6   5  4  3   2  1  0
               +----------------------------------------------------+
       '20 ST1 |   ARB  |CNF|TC|SXM| 1| 1  1| 1|  1|XF|FO|TXM|  PM  |
               +----------------------------------------------------+

                15 14 13  12 11  10  9  8  7  6   5  4  3   2  1  0
               +----------------------------------------------------+
      'C25 ST1 |   ARB  |CNF|TC|SXM| C| 1  1|HM|FSM|XF|FO|TXM|  PM  |
               +----------------------------------------------------+


      ARB   Auxiliary Register Pointer Buffer. Whenever the ARP is loaded,
            the old ARP value is copied to the ARB except during a LST
            instruction. When the ARB is loaded via the LST1 instruction,
            the same value is copied to the ARP.

      ARP   Auxiliary Register Pointer. This three-bit field selects the
            AR to be used in indirect addressing. When ARP is loaded, the
            old ARP value is copied to the ARB register. ARP may be
            modified by memory-reference instructions when using indirect
            addressing, and by LARP, MAR, and LST instructions. ARP is
            also loaded with the same value as ARB when an LST1
            instruction is executed.

      C     Carry bit (TMS320C25). This bit is set to one if the result
            of an addition generates a carry, or reset to zero if the
            result of a subtraction generates a borrow. Otherwise, it is
            reset after an addition or set after a subtraction, except if
            the instruction is a ADDH or a SUBH. ADDH can only set and
            SUBH can only reset the carry bit, but cannot affect it
            otherwise. The shift and rotate functions also affect this
            bit, as well as the SC, RC, and LST1 instructions. Two branch
            instructions, BC and BNC have been provided to branch on the
            status of C. C is set to one on a reset.

      CNF   On-chip RAM Configuration Control bit. If set to 0, block B0
            is configured as data memory; otherwise, block B0 is
            configured as program memory. The CNF may be modified by CNFD,
            CNFP, and LST1 instructions. Reset makes CNF zero.

      DP    Data Memory Page Pointer. The nine-bit DP register is
            concatenated with the seven LSB's of an instruction word to
            form a direct memory address of 16 bits. DP may be modified
            by the LST, LDP, and LDPK instructions.

      FO    Format bit. When set to zero, the serial port registers are
            configured as 16-bit registers. When set to one, the port
            registers are configured to transmit/receive 8-bit bytes. FO
            may be modified by the FORT and LST1 instructions. FO is reset
            to zero.

      FSM   Frame Synchronization Mode bit. This bit indicates whether or
            not the serial port operates with or without frame
            synchronization pulses. When FSM = 1, the serial port
            operation is initiated following a frame sync pulse on the
            FSX/FSR inputs. When FSM = 0, the FSX/FSR inputs are ignored
            and the serial port operates continuously with no frame sync
            pulses required. The bit is set to one by a reset.
                                            __
      HM    Hold Mode bit (TMS320C25). When HM = 1, the processor halts
            internal execution when acknowledging an active HOLD. When HM
            = 0, the processor may continue execution out of internal
            program memory but puts its external interface in a high-
            impedance state. The bit is set to one by a reset.

      INTM  Interrupt Mode bit. When set to zero, all unmasked interrupts
            are enabled. When set to one, are maskable interrupts are
            disabled. INTM is set and reset by the DINT and EINT
                          __     ____
            instructions. RS and IACK also set INTM. INTM has no affect
                              __
            on the unmaskable RS interrupt. Note that INTM is unaffected
            by the LST instruction.

      OV    Overflow flag bit. As a latched overflow signal, OV is set to
            one when overflow occurs in the ALU. Once an overflow occurs,
            the OV remains set until a reset, BV, BNV, or LST instruction
            clears the OV.

      OVM   Overflow Mode bit. When set to zero, overflowed results
            overflow normally in the accumulator. When set to one, the
            accumulator is set to either its most positive or negative
            value upon encountering an overflow. The SOVM and ROVM
            instructions set and reset this bit, respectively. LST may
            also be used to modify the OVM.

      PM    Product Shift Mode. If the two bits are 00, the multiplier's
            32-bit productis loaded into the ALU with no shift. If PM =
            01, the PR output is left-shifted one place and loaded into
            the ALU, with the LSB's zero-filled. If PM = 10, the PR output
            is left-shifted by four bits and loaded into the ALU, and the
            LSB's zero-filled. PM = 11 produces a right-shift of six bits,
            sign-extended. Note that the PR contents remain unchanged. The
            shift takes place when transferring the contents of the PR to
            the ALU. PM is loaded by the SPM and LST1 instructions. The
            PM bits are cleared by a reset signal.

      SXM   Sign-Extension Mode bit. SXM = 1 produces sign-extension on
            data as it is passed into the accumulator through the scaling
            shifter. SXM = 0 suppresses sign-extension. SXM does not
            affect the definition of certain instructions; e.g., the ADDS
            instruction suppresses sign-extension regardless of SXM. This
            bit is set and reset by the SSXM and RSXM instructions, and
            may also be loaded by LST1. SXM is set to one by a reset.

      TC    Test/Control Flag bit. The TC bit is affected by the BIT,
            BITT, CMPR, LST1 and NORM instructions. The TC bit is set to
            one if a bit tested by BIT or BITT is one, if a compare
            condition tested by the CMPR exists between AR0 and another
            AR pointed to by the ARP, or if the exclusive-OR function of
            the two MSB's of the accumulatoris true when tested by the
            NORM instruction. Two branch instructions, BBZ and BBNZ,
            provide branching on the status of the TC.

      TXM   Transmit Mode bit. TXM = 1 configures the serial port's FSX
            pin to be an output. In this mode, a pulse is produced on FSX
            when DXR is loaded. Transmission then starts on the DX pin.
            TXM = 0 configures the FSX pin to be an input. TXM is set and
            reset by the STXM and RTXM instructions and may also be loaded
            by LST1. Reset makes TXM = 0.

      XF    XF pin status bit. This status bit indicates the state of the
            XF pin. XF is set and reset by the SXF and RXF instructions
            or may be loaded by LST1. XF is set to one by a reset signal.