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SYNTAX      DIRECT   [<LABEL>] SST <dma>
            INDIRECT [<LABEL>] SST {ind}[,<next ARP>]

OPERANDS    0 . dma . 127; 0 . next ARP . 7.

EXECUTION   (PC) + 1 . PC
            (status register ST0) . dma

DESCRIPTION Status register ST0 is stored in data memory.

            In the direct addressing mode, status register ST0 is always
            stored in page 0 regardless of the value of the DP register.
            The processor automatically forces the page to be 0, and the
            specific location within that page is defined in the
            instruction. Note that the DP register is not physically
            modified. This allows storage of the DP register in the data
            memory on interrupts, etc., in the direct addressing mode
            without having to change the DP. In the indirect addressing
            mode, the data memory address is obtained from the auxiliary
            register selected. See the LST instruction for more
            information.

            The SST instruction can be used to store status register ST0
            after interrupts and subroutine calls. The ST0 contains the
            status bits: OV (overflow flag) bit, OVM (overflow mode) bit,
            INTM (interrupt mode) bit, ARP (auxiliary register pointer)
            bit, and DP (data memory page pointer) bits. The status bits
            are stored in the data memory word as follows:

                  15 14 13 12  11 10    9  8  7  6  5  4  3  2  1  0
                  +-------------------------------------------------+
                  |  ARP  |OV|OVM| 1|INTM|            DP            |
                  +-------------------------------------------------+


            Note that SST * may be used to store status register ST0
            anywhere in data memory, while SST in the direct addressing
            mode is forced to page 0.

WORDS       1

ENCODING    15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |0  1  1  1  1  0  0  0| 0| data memory address | DIRECT
            +-----------------------------------------------+

            15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |0  1  1  1  1  0  0  0| 1| see indirect fields | INDIRECT
            +-----------------------------------------------+

CYCLES

            +------------------------------------------------+
            |    Cycle Timings for a Single Instruction      |
            |------------------------------------------------|
            | PI/DI | PI/DE | PE/DI | PE/DE  | PR/DI | PR/DE |
            |-------+-------+-------+--------+-------+-------|
      '20   |   1   |  2+d  |  1+p  | 3+d+p  |   -   |   -   |
            |-------+-------+-------+--------+-------+-------|
     'C25   |   1   |  1+d  |  1+p  | 2+d+p  |   1   |  2+d  |
            |------------------------------------------------|
            |    Cycle Timings for a Repeat Instruction      |
            |------------------------------------------------|
      '20   |   n   | 2n+nd |  n+p  | 3n+nd+p|   -   |   -   |
            |-------+-------+-------+--------+-------+-------|
     'C25   |   n   | n+nd  |  n+p  |1+n+nd+p|   n   | n+nd  |
            +------------------------------------------------+



EXAMPLE     SST   DAT96       (DP = any)
            or
            SST   *           If current auxiliary register contains 96.

                          BEFORE                    AFTER

            Status Register         Status Register
                        ST0 >A408               ST0 >A408
                       dm96    >A              dm96 >A408