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SYNTAX      DIRECT   [<LABEL>] SST1 <dma>
            INDIRECT [<LABEL>] SST1 {ind}[,<next ARP>]

OPERANDS    0 . dma . 127; 0 . next ARP . 7.

EXECUTION   (PC) + 1 . PC
            (status register ST1) . dma

DESCRIPTION Status register ST1 is stored in data memory.

            In the direct addressing mode, status register ST1 is always
            stored in page 0 regardless of the value of the DP register.
            The processor automatically forces the page to be 0, and the
            specific location within that page is defined in the
            instruction. Note that the DP register is not physically
            modified. This allows storage of the DP register in the data
            memory on interrupts, etc., in the direct addressing mode
            without having to change the DP. In the indirect addressing
            mode, the data memory address is obtained from the auxiliary
            register selected. See the LST instruction for more
            information.

            The SST1 instruction can be used to store status bits after
            interrupts and subroutine calls. The ST1 contains the status
            bits: ARB (auxiliary register pointer buffer) CNF (RAM
            configuration control) bit, T/C (test/control) bit, SXM (sign-
            extension mode) bit, XF (external flag) bit, FO (serial port
            format) bit, TXM (transmit mode) bit, and the PM (product
            register shift mode) bit. ST1 on the TMS320C25 also contains
            the status bits: C (carry) bit, HM (hold mode) bit, and FSM
            (frame synchronization mode) bit. The bits loaded into status
            register ST1 from the data memory word are:

                  15 14 13  12 11  10  9  8  7  6  5  4  3   2  1  0
                  +-------------------------------------------------+
              '20 |  ARB  |CNF|TC|SXM| 1  1  1  1  1|XF|FO|TXM| PM  |
                  +-------------------------------------------------+
                  15 14 13  12 11  10  9  8  7  6   5  4  3   2  1  0
                  +--------------------------------------------------+
             'C25 |  ARB  |CNF|TC|SXM| C| 1  1|HM|FSM|XF|FO|TXM| PM  |
                  +--------------------------------------------------+


            Note that SST1 * may be used to store status register ST1
            anywhere in data memory, while SST1 in the direct addressing
            mode is forced to page 0.

WORDS       1

ENCODING    15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |0  1  1  1  1  0  0  1| 0| data memory address | DIRECT
            +-----------------------------------------------+

            15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |0  1  1  1  1  0  0  1| 1| see indirect fields | INDIRECT
            +-----------------------------------------------+

CYCLES

            +------------------------------------------------+
            |    Cycle Timings for a Single Instruction      |
            |------------------------------------------------|
            | PI/DI | PI/DE | PE/DI | PE/DE  | PR/DI | PR/DE |
            |-------+-------+-------+--------+-------+-------|
      '20   |   1   |  2+d  |  1+p  | 3+d+p  |   -   |   -   |
            |-------+-------+-------+--------+-------+-------|
     'C25   |   1   |  1+d  |  1+p  | 2+d+p  |   1   |  2+d  |
            |------------------------------------------------|
            |    Cycle Timings for a Repeat Instruction      |
            |------------------------------------------------|
      '20   |   n   | 2n+nd |  n+p  | 3n+nd+p|   -   |   -   |
            |-------+-------+-------+--------+-------+-------|
     'C25   |   n   | n+nd  |  n+p  |1+n+nd+p|   n   | n+nd  |
            +------------------------------------------------+



EXAMPLE     SST1  DAT97       (DP = any)
            or
            SST1  *           If current auxiliary register contains 97.

                          BEFORE                    AFTER

            Status Register         Status Register
                        ST1 >A7E0               ST1 >A7E0
                       dm97    >B              dm97 >A7E0