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      The TMS320C2x utilizes a 16 * 16-bit hardware multiplier, which is
      capable of computing a signed or unsigned 32-bit product in a single
      machine cycle. All multiply instructions, except the MPYU (multiply
      unsigned) instruction on the TMS320C25, perform a signed multiply
      operation in the multiplier. That is, the two numbers being
      multiplied are treated as two's-complement numbers, and the result
      is a two's-complement 32-bit number. The following two registers are
      associated with the multiplier:

            1) A 16-bit temporary register (TR)that holds on e of the
            operands for the multiplier, and
            2) A 32-bit product register (PR) that holds the product.

      The output of the product register can be left-shifted one or four
      bits. This is useful for implementing fractional arithmetic or
      justifying fractional products. The output of the PR can also be
      right-shifted 6-bits to enable the execution of up to 128
      consecutive multiply/accumulates without the possibility of
      overflow.

      An LT (load T register) instruction normally loads the TR to provide
      one operand (from the data bus), and MPY (multiply) instruction
      provides the second operand (also from the data bus). A
      multiplication can also be performed with an immediate operand using
      the MPYK instruction. In either case, a product can be obtained
      every two cycles.

      Two multiply/accumulate instructions (MAC and MACD) fully utilize
      the computational bandwidth of the multiplier, allowing both
      operands to be processed simueltaneously. The data for these
      operations may reside anywhere in internal or external memory, or
      can be transferred to the multiplier each cycle via the program and
      data buses. This provides for single-cycle multiply/accumulates when
      used with repeat (RPT/RPTK) instructions. Note that the DMOV portion
      of the MACD instruction will not function with external data memory
      addresses. On the TMS32020, the multiplier and the multiplicand must
      reside in separate on-chip RAM blocks. On the TMS320C25, the MAC and
      MACD instructions can be used with both operands in either internal
      or external memory or one each in on-chip RAM. The SQRA (square/add)
      and SQRS (square/subtract) instructions pass the same value to both
      inputs of the multiplier for squaring a data memory value.

      The MPYU instruction on the TMS320C25 performs an unsigned
      multiplication, which greatly facilitates extended-precision
      arithmetic operations. The unsigned contents of the T register are
      multiplied by the unsigned contents of the addressed data memory
      location, with the result placed in the P register. This allows
      operands of greater than 16 bits to be broken down into 16-bit words
      and processed separately to generate products of greater than 32-
      bits.

      After the multipliplication of two 16-bit numbers, the 32-bit
      product is loaded into the 32-bit product register (PR) on the
      TMS320C2x. The product from the PR may be transferred to the ALU.

      Four product shift modes (PM) are available at the product register
      (PR) output, which are useful when performing multiply/accumulate
      operations, fractional arithmetic, or justifying fractional
      products. The PM field of status register ST1 specifies the PM shift
      mode:

                  PM                Result
                  00          No shift
                  01          Left shift of one bit
                  10          Left shift of four bits
                  11          Right shift of six bits

      Left shifts specified by the PM value are useful for implementing
      fractional arithmetic or justifying fractional products. For
      example, the product of either two normalized, 16-bit, two's-
      complement numbers or two Q15 numbers contains two sign bits, one
      of which is redundant. Q15 format, one of the various types of Q
      format, is a number representation commonly used when performing
      operations on non-integer numbers.  In Q format, Q<number>, <number>
      denotes how many digits are located to the right of the binary
      point. A 16-bit number in Q15 format, therefore, has an assumed
      binary point immediately to the right of the most significant bit.
      Since the most significant bit constitutes the sign of the number,
      then numbers represented in Q15 may take on values from +1
      (represented by 0.99997) to -1. Thus a single bit left shift
      eliminates the extra sign bit from the product when it is
      transferred to the accumulator. This results in the accumulator
      being formatted in the same manner as the multiplicands. Similarly,
      the product of either a normalized, 16-bit, two's-complement or Q15
      number and a 13-bit, two's-complement constant contains five sign
      bits, four of which are redundant. This is the case, for example,
      when using the MPYK instruction. Here the four-bit shift properly
      aligns the result as it is transferred to the accumulator.

      Use of the right-shift PM value allows the execution of up to 128
      consecutive multiply/accumulate operations without the threat of an
      arithmetic overflow, thereby avoiding the overhead of overflow
      management. The shifter can be disabled to cause no shift in the
      product when working with integer or 32-bit precision operations.
      This allows compatibility with TMS320C1x code to be maintained. Note
      that the PM right shift is always sign-extended regardless of the
      state of SXM.

      The four least significant bits of the T register (TR) also define
      a variable shift through the scaling shifter for the LACT/ADDT/SUBT
      (load/add to/subtract from accumulator with shift specified by the
      TR) instructions. These instructions are useful in floating-point
      arithmetic where a number needs to be denormalized, i.e., floating-
      point to fixed-point conversion. The BITT (bit test) instruction
      allows testing of a single bit of a word in data memory based on the
      value contained in the four LSB's of the TR.