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      The TMS320C2x Central Arithmetic Logic Unit (CALU) contains a 16-
      bit scaling shifter, a 16 * 16-bit parallel multiplier, a 32-bit
      Arithmetic Logic Unit (ALU), a 32-bit accumulator and additional
      shifters at the outputs of both the accumulator and the multiplier.

      The following steps occur in the implementation of a typical ALU
      instruction:

            1) Data is fetched from the RAM on the data bus,
            2) Data is passed through the scaling shifter and the
            ALU where the arithmetic is performed, and
            3) The result is moved into the accumulator.

      One input to the ALU is always provided from the accumulator, and
      the other input may be transferred from the Product Register (PR)
      of the multiplier or from the scaling shifter that is loaded from
      data memory.