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      The TMS320C2x 32-bit ALU and accumulator implement a wide range of
      arithmetic and logic functions, the majority of which execute in a
      single clock cycle. Once an operation is performed in the ALU, the
      result is transferred to the accumulator where additional operations
      such as shifting may occur. Data that is input to the ALU may be
      scaled by the scaling shifter.

      The ALU is a general-purpose arithmetic unit that operates on  16-
      bit words taken from the data RAM or derived from immediate
      instructions. In addition to the usual arithmetic instructions, the
      ALU can perform Boolean operations, providing the bit manipulation
      ability required a high-speed controller. One input to the ALU is
      always provided by the accumulator, and the other input may be
      provided by the product register (PR) of the multiplier or the input
      scaling shifter that has fetched data from the RAM on the data bus.
      After the ALU has performed the arithmetic or logical operations,
      the result is stored in the accumulator.

      The 32-bit accumulator is split into two 16-bit segments for storage
      in data memory: ACCH (accumulator high) and ACCL (accumulator low).
      Shifters at the output of the accumulator provide a left-shift of
      0 to 7 places on the TMS320C25 or 0, 1, or 4 places on the TMS32020.
      This shift is performed while the data is being transferred to the
      data bus for storage. The contents of the accumulator remain
      unchanged. When the ACCH data is shifted left, the LSB's are
      transferred from the ACCL, and the MSB's are lost. When ACCL is
      shifted left, the LSB's are zero-filled, and the MSB's are lost.

      The TMS320C2x supports floating-point operations for applications
      requiring a large dynamic range. The NORM (normaliztion) instruction
      is used to normalize fixed point numbers contained in the
      accumulator by performing left shifts. The LACT (load accumulator
      with shift specified by the T register) instruction denormalizes a
      floating-point number by arithmetically left-shifting the mantissa
      through the input scaling shifter. The shift count, in this case,
      is the value of the exponent specified by the four low-order bits
      of the T register (TR). ADDT and SUBT (add/subtract  from
      accumulator with shift specified by T register) instructions have
      also been provided to allow additional arithmetic operations.

      The accumulator overflow saturation mode may be programmed through
      the SOVM and ROVM (set/reset overflow mode) instructions. When the
      accumulator is in the overflow saturation mode and an overflow
      occurs, the overflow flag is set and the accumulator is loaded with
      either the most positive or the most negative number depending upon
      the direction of the overflow. The value of the accumulator upon
      saturation is >7FFFFFFF (positive) or >80000000 (negative). If OVM
      (overflow mode) status register bit is reset and an overflow occurs,
      the overflowed results are loaded into the accumulator without
      modification. Note that logical operands cannot result in overflow.

      The TMS320C2x can execute a variety of branch instructions that
      depend on the status of the ALU and accumulator. These instructions
      include the BV (branch on overflow) and BZ (branch on accumulator
      equal to zero). In addition, the BACC (branch to address in
      accumulator) instruction provides the ability to branch to an
      address specified by the accumulator. Bit test instructions (BIT and
      BITT), which do not affect the accumulator, allow the testing of a
      specified bit of a word in data memory.

      The accumulator on the TMS320C25 also has an associated carry bit
      that is set or reset depending on various operations within the
      device. The carry bit allows more efficient computation of extended-
      precision products and additions or subtractions. It is also useful
      in overflow management. The carry bit is affected by most arithmetic
      instructions as well as the shift and rotate instructions. It is not
      affected by loading the accumulator, logical operations, or other
      such non-arithmetic or control instructions. It is also not affected
      by the multiply (MPY, MPYK, and MPYU) instructions, but is affected
      by the accumulation process in the MAC and MACD instructions.
      Examples of carry bit (TMS320C25) operation:

      C  MSB                LSB           C  MSB                LSB
      X  F  F  F  F  F  F  F  F ACC       X  0  0  0  0  0  0  0  0 ACC
        +                     1             -                     1
        -----------------------             -----------------------
      1  0  0  0  0  0  0  0  0           0  F  F  F  F  F  F  F  F


      C  MSB                LSB           C  MSB                LSB
      X  7  F  F  F  F  F  F  F ACC       X  8  0  0  0  0  0  0  0 ACC
        +                     1 OVM=0       -                     1 OVM=0
        -----------------------             -----------------------
      0  8  0  0  0  0  0  0  0           1  7  F  F  F  F  F  F  F

      C  MSB                LSB           C  MSB                LSB
      1  0  0  0  0  0  0  0  0 ACC       0  F  F  F  F  F  F  F  F ACC
        +                     0 ADDC        -                     0 SUBB
        -----------------------             -----------------------
      0  0  0  0  0  0  0  0  1           1  F  F  F  F  F  F  F  E


      The value added to or subtracted from the accumulator, shown above,
      may come from either the input scaling shifter or the shifter at the
      output of the P register. The carry bit is set if the result of an
      addition or accumulation process results in a carry, or reset to
      zero if the result of a subtraction generates a borrow; otherwise,
      it is reset after an addition or set after a subtraction.

      The ADDC (add to accumulator with carry) and SUBB (subtract from
      accumulator with borrow) instructions provided on the TMS320C25 use
      the previous value of carry in their addition/subtraction operation.

      The one exception to operation of the carry bit is the use of the
      ADDH (add to high accumulator) and SUBH (subtract from high
      aaccumulator) instructions. The ADDH instruction can only set the
      carry bit if a carry is generated, and the SUBH instruction can only
      reset the carry bit if a borrow is generated; otherwise, neither
      instruction can affect the carry bit.

      Two branch instructions, BC and BNC, have been provided for
      branching on the status of the carry bit. The SC, RC, and LST1
      instructions can also be used to load the carry bit. The carry bit
      is set to one on a hardware reset.

      The SFL and SFR (in-place one-bit shift to the left/right)
      instructions on the TMS320C2x and the ROL and ROR (rotate
      left/right) instructions on the TMS320C25 implement shifting or
      rotating of the contents of the accumulator through the carry bit.
      The SXM bit affects the definition of the SFR (shift accumulator
      right) instruction. When SXM = 1, SFR performs an arithmetic right
      shift, maintaining the sign of the accumulator data. When SXM = 0,
      SFR performs a logical shift, shifting out the LSB and shifting in
      a zero for the MSB. The SFL (shift accumulator left) instruction is
      not affected by the SXM bit and behaves the same in both cases,
      shifting out the MSB and shifting in a zero. Repeat (RPT or RPTK)
      instructions may be used with the shift and rotate instructions for
      multiple shift counts.