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      The large amount of external memory and the configurability of on-
      chip RAM simplify the downloading of data or program memory into the
      TMS320C2x. Also, since data in RAM is preserved when re-defining on-
      chip RAM, block B0 can be configured dynamically as either data or
      program memory.

      On-chip memory is configured by a reset or by the CNFD and CNFP
      instructions. Block B0 is configured as data memory by executing a
      CNFD or reset. A CNFP instruction configures block B0 as program
      memory.

      Configuring block B0 as program memory is useful for implementing
      adaptive filters or similar applications at full speed with only on-
      chip memories. The following example illustrates the use of the
      configuration modes to utilize block B0 as data and program memory
      while executing from on-chip program ROM.

      .title        'ADAPTIVE FILTER'
      .def   ADPFIR
      .def   X,Y
*
* 128-TAP ADAPTIVE FIR FILTER
*   USES ON-CHIP MEMORY (BLOCK B0) FOR COEFFICIENTS
*   USES ON-CHIP MEMORY (BLOCK B1) FOR DATA SAMPLES
*   NEWEST INPUT SHOULD BE IN MEMORY LOCATION X WHEN CALLED
*   OUTPUT WILL BE IN MEMORY LOCATION Y WHEN RETURNED
*
COEFFP: .set       0ff00h     ; B0 PROGRAM MEMORY ADDRESS
COEFFD: .set       0200h      ; B0 DATA MEMORY ADDRESS
*
ONE:    .set       07ah       ; CONSTANT ONE          (DP=6)
BETA:   .set       07bh       ; ADAPTATION CONSTANT   (DP=6)
ERR:    .set       07ch       ; SIGNAL ERROR          (DP=6)
ERRF:   .set       07dh       ; ERROR FUNCTION        (DP=6)
Y:      .set       07eh       ; FILTER OUTPUT         (DP=6)
X:      .set       07fh       ; NEWEST DATA SAMPLE    (DP=6)
FRSTAP: .set       0380h      ; NEXT NEWEST DATA SAMPLE
LASTAP: .set       03ffh      ; OLDEST DATA SAMPLE
*
* FINITE IMPULSE RESPONSE (FIR) FILTER
*
ADPFIR      CNFP              ; CONFIGURE B0 AS PROGRAM
            MPYK  0           ; clear the P-register
            LAC   ONE,14      ; load output rounding bit
            LARP  AR3
            LRLK  AR3,LASTAP  ; point to the oldest sample
FIR         RPTK  127
            MACD  COEFFP,*-   ; 128-tap FIR filter
            CNFD              ; CONFIGURE B0 AS DATA
            APAC
            SACH  Y,1         ; store the filter output
            NEG
            ADD   X,15        ; add the newest input
            SACH  ERR,1       ; err(n) = x(n) - y(n)
*
* LMS ADAPTATION OF FILTER COEFFICIENTS
*
            LT    ERR
            MPY   BETA
            PAC               ; errf(n) = beta * err(n)
            ADD   ONE,14      ; round the result
            SACH  ERRF,1
*
            LARP  AR3
            LARK  AR1,127     ; 128 coefficients to update
            LRLK  AR2,COEFFD  ; point to the coefficients
            LRLK  AR3,LASTAP  ; point to the data samples
            DMOV  X           ; include newest sample
            LT    ERRF
            MPY   *-,AR2      ; P=2*beta*err(n)*x(n-k)
*
ADAPT       ZALR  *,AR3       ; load ACCH with ak(n) & rnd
            MPYA  *-,AR2      ; ak(n+1)=ak(n)+P
*                             ; P=2*beta*err(n)*x(n-k)
            SACH  *+,0,AR1    ; store ak(n+1)
            BANZ  ADAPT,*-,AR2      ; end of loop test
*
            RET               ; return to calling routine


      In using on-chip memory (block B0) for program execution, this
      memory must first be loaded with executable code from external
      memories while configured as data memory. On-chip execution is
      initiated by using the CNFP instruction to reconfigure block B0 as
      program memory and performing a branch or a call to an on-chip RAM
      address. By configuring block B0 as program memory and executing
      from this internal memory, full speed execution can be achieved in
      systems user slower external memory.

      One group of instructions, the branch/call instructions, are
      impacted by the location of execution. Normally, by using labels,
      the assembler properly determines the location to which a branch is
      taken. Since the code is relocated prior to execution from on-chip
      memory, it is necessary to alter the address determined by the
      assembler for branch instructions. The alteration is necessary so
      that the branch address that is determined can be consistent with
      the address space being during execution.