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PSRLW           Packed Shift Right Logical, Word

PSRLW destination, count                             CPU: MMX

        Logic   mm(15..0)  <- mm(15..0)  SHR count
                mm(31..16) <- mm(31..16) SHR count
                mm(47..32) <- mm(47..32) SHR count
                mm(63..48) <- mm(63..48) SHR count

    PSRLW performs a shift-logical-right operation on each of the four
    words in the destination operand. The count operand determines how
    many bits to right-shift. The new high-order bits are cleared (set
    to zero).
    If the value specified by the count operand is greater than 15 (0Fh)
    the destination is set to all zeros. 

    The destination operand is an MMX register. The count operand (source
    operand) can be either an MMX register, a 64-bit memory operand, or
    an immediate 8-bit operand.


    Opcode      Format
    0F D1 /r    PSRLW mm, mm/m64
    0F 71 /2 ib PSRLW mm, imm8