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PSRLQ           Packed Shift Right Logical, Quadword

PSRLQ destination, count                             CPU: MMX

        Logic   mm <- mm SHR count

    PSRLQ performs a shift-logical-right operation on the quardword
    destination operand. The count operand determines how many bits to
    right-shift. The new high-order bits are cleared (set to zero).
    If the value specified by the count operand is greater than 63 (3Fh)
    the destination is set to all zeros.

    The destination operand is an MMX register. The count operand (source
    operand) can be either an MMX register, a 64-bit memory operand, or
    an immediate 8-bit operand.


    Opcode      Format
    0F D3 /r    PSRLQ mm, mm/m64
    0F 73 /2 ib PSRLQ mm, imm8