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      The exact sequence of operations performed as instructions execution
      depends on the areas of memory where the instruction operands are
      located. There are six possible combinations of progaram and data
      memory since the information can be located in either internal RAM,
      external memory, or internal ROM (TMS320C25). The six possible
      combinations are:
            Program Internal RAM/Data Internal (PI/DI)
            Program Internal RAM/Data External (PI/DE)
            Program External/Data Internal (PE/DI)
            Program External/Data External (PE/DE)
            Program Internal ROM/Data Internal (PR/DI) TMS320C25
            Program Internal ROM/Data External (PR/DE) TMS320C25

PI/DI       When both program and data memory are on-chip, the processor
or PR/DI    runs at full speed with no wait states. Note that IN and OUT
            instructions have different cycle timings when program memory
            is internal; IN requires two cycles whereas OUT requires only
            one cycle.

PE/DI       This memory mode can run at full speed if external program
            memory is sufficiently fast since internal data operations can
            occur coincident with external program memory accesses. If
            external program memory is not fast enough, wait states may
            generated using the READY input.

PI/DE,      Additional cycles are required to execution instructions that
PE/DE,      reference an external data memory space. At least two cycles
or PR/DE    are required to execute "read from external data memory"
            instructions such as ADD, LAR, etc. Further additional cycles
            may be required due to wait states if external data memory is
            not fast enough to accessed within a single cycle. Note that
            the TMS320C25 has the capability of executing "write to
            external data memory" instructions in a single cycle when
            program memory is internal (two cycles are required if program
            memory is also to be external). Additional cycles are also
            required in this case if external data memory is not
            sufficiently fast.

      In all memory configurations where the same bus is used to
      communicate with external data, program, or I/O space, the number
      of cycles required to execute a particular instruction may further
      vary depending on whether the next instruction fetch is from
      internal or external program memory.