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The TMS320C2x provides a total of 544 16-bit words of on-chip data
RAM, of which 288 words are always data memory and the remaining 256
words may be configured as either program or data memory. The
TMS320C25 also provides 4K words of maskable program ROM.
MEMORY MAPS
The TMS320C2x provides three separate address spaces for program
memory, data memory, and I/O as shown below. These spaces are
distinguished externally by means of the
__ __ __
PS, DS, and IS (program, data, and I/O space select) signals.
__ __ __ ____
The PS, DS, IS, and STRB signals are only active when external
memory is being addressed. During an internal addressing cycle,
these signals remain inactive high, thus preventing conflicts in
memory addressing, e.g., when block B0 is configured as program
memory.
The on-chip memory blocks B0, B1, and B2 are comprised of a total
of 544 words of RAM. Program/data RAM block B0 (256 words) resides
in pages 4 and 5 of the data memory map when configured as data RAM
and at addresses >FF00 to >FFFF when configured as program RAM.
Block B1 (always data RAM) resides in pages 6 and 7, while block B2
resides in the upper 32 words of page 0. Note that the remainder of
page 0 is composed of the memory-mapped registers and internally
reserved locations, and pages 1-3 of the data memory map consist of
internally reserved locations. The internally reserved locations may
not be used for storage, and their contents are undefined when read.
See also "memory-mapped registers".
The on-chip RAM is mapped into either the 64K-word data memory or
program memory space, depending on the memory configuration. The
CNFD/CNFP instructions are used to configure block B0 as either data
or program memory, respectively. The BLKP (block move from program
memory to data memory) instruction may be used to download program
information to block B0 when it is configured as data RAM. Then a
CNFP (configure block as program memory) instruction may be used to
convert it to program RAM (see also "memory management"). Regardless
of the configuration, the user may still execute from external
program memory. Note that when accessing internal program memory,
external control lines remain inactive.
Reset configures block B0 as data RAM. Due to internal pipelining,
when CNFD or CNFP instruction is used to remap RAM block B0, there
is a delay before the new configuration becomes effective. This
delay is one fetch cycle if execution is from internal program RAM.
On the TMS32020, adelay of one fetch cycle occurs if execution is
from internal program memory. On the TMS320C25, there is a delay of
two fetch cycles if execution is from ROM or external program
memory. This is particularly important if program execution is from
the locations around >FF00. Accordingly, a CNFP instruction must
be placed at program location >FEFD in external memory if execution
is to continue from the first location in block B0. If a CNFP is
placed at location >FEFD, and the instruction at >FEFF is a two-word
instruction, the second word of the instruction will be fetched from
the first location in block B0. If execution is from above location
>FF00 and block B0 is reconfigured, care must be taken to assure
that execution resumes at the apprpriate point in a new
configuration.
On-chip program ROM on the TMS320C25 is located in the lower 4K
words of program memory when selected by setting
__ __
MP/MC = 0. When MP/MC = 1, the lower 4K words of program memory are
external.
MEMORY MAPS AFTER CNFD INSTRUCTION
PROGRAM PROGRAM DATA
>0000+--------------+ >0000+--------------+ >0000+--------------+
| INTERRUPTS | | INTERRUPTS | | ON-CHIP |
| AND RESERVED | | AND RESERVED | | MEMORY-MAPPED|
>001F| (EXTERNAL) | >001F|(ON-CHIP ROM) | | REGISTERS |
|--------------| |--------------| >0005|--------------|
>0020| | >0020| ON-CHIP | >0006| RESERVED |PG 0
| | >0FAF| ROM | >005F|--------------|
| | |--------------| >0060| ON-CHIP |
| | >0FB0| RESERVED | >007F| BLOCK B2 |
| | >0FFF| | >0080|--------------|
| | |--------------| >01FF| RESERVED |PG1-3
| | >1000| | |--------------|
| EXTERNAL | | | >0200| ON-CHIP |
| | | | >02FF| BLOCK B0 |PG4-5
| | | EXTERNAL | |--------------|
| | | | >0300| ON-CHIP |
| | | | >03FF| BLOCK B1 |PG6-7
| | | | |--------------|
| | | | >0400| |PG 8-
| | | | | EXTERNAL | 511
>FFFF+--------------+ >FFFF+--------------+ >FFFF+--------------+
IF MP/MC = 1 IF MP/MC = 0
TMS320C25 ONLY
MEMORY MAPS AFTER CNFP INSTRUCTION
PROGRAM PROGRAM DATA
>0000+--------------+ >0000+--------------+ >0000+--------------+
| INTERRUPTS | | INTERRUPTS | | ON-CHIP |
| AND RESERVED | | AND RESERVED | | MEMORY-MAPPED|
>001F| (EXTERNAL) | >001F|(ON-CHIP ROM) | | REGISTERS |
|--------------| |--------------| >0005|--------------|
>0020| | >0020| ON-CHIP | >0006| RESERVED |PG 0
| | >0FAF| ROM | >005F|--------------|
| | |--------------| >0060| ON-CHIP |
| | >0FB0| RESERVED | >007F| BLOCK B2 |
| | >0FFF| | >0080|--------------|
| | |--------------| >01FF| RESERVED |PG1-3
| | >1000| | |--------------|
| EXTERNAL | | | >0200| DOES NOT |
| | | | >02FF| EXIST |PG4-5
| | | EXTERNAL | |--------------|
| | | | >0300| ON-CHIP |
>FEFF| | >FEFF| | >03FF| BLOCK B1 |PG6-7
|--------------| |--------------| |--------------|
>FF00| ON-CHIP | >FF00| ON-CHIP | >0400| |PG 8-
| BLOCK B0 | | BLOCK B0 | | EXTERNAL | 511
>FFFF+--------------+ >FFFF+--------------+ >FFFF+--------------+
IF MP/MC = 1 IF MP/MC = 0
TMS320C25 ONLY