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      For multi-processing applications, the TMS320C2x has the capability
                                                     __
      of allocating global data memory space via the BR (bus request) and
      READY control signals.

      Global memory is memory shared by more than one processor;
      therefore, access to it must be arbitrated. When using global
      memory, the processor's address space is divided into local and
      global sections. The local section is used by the processor to
      perform its individual function, and the global section is used to
      communicate with other processors.

      A memory-mapped global memory allocation register (GREG) specifies
      part of the TMS320C2x data memory as global external memory. GREG,
      which is memory-mapped at data memory location 5, is an 8-bit
      register connected to the 8-LSB's of the internal D bus. The upper
      8 bits of location 5 are non-existent and read as one's.

      The contents of GREG determine the size of the global memory space.
      The legal values of GREG and corresponding global memory spaces
      follow; note that values other than those listed lead to fragmented
      memory maps.

                           Local Memory               Global Memory
      GREG Value       Range        # Words       Range        # Words
      0000 00XX      >0 - FFFF      65,536      ---------           0
      1000 0000      >0 - 7FFF      32,768      >8000 - >FFFF  32,768
      1100 0000      >0 - BFFF      49,152      >C000 - >FFFF  16,384
      1110 0000      >0 - DFFF      57,344      >E000 - >FFFF   8,192
      1111 0000      >0 - EFFF      61,440      >F000 - >FFFF   4,096
      1111 1000      >0 - F7FF      63,488      >F800 - >FFFF   2,048
      1111 1100      >0 - FBFF      64,512      >FC00 - >FFFF   1,024
      1111 1110      >0 - FDFF      65,024      >FE00 - >FFFF     512
      1111 1111      >0 - FEFF      65,280      >FF00 - >FFFF     256

      When a data memory address, either direct or indirect, corresponds
      to a global data memory address (as defined by GREG),
      __                      __
      BR is asserted low with DS to indicate that the processor wishes to
      make a global memory access. External logic then arbitrates for
      control of the global memory, asserting READY when the TMS320C2x has
      control. The length of the memory cycle is controlled by the READY
      line.