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      Interrupts on the TMS320C2x are prioritized in hardware. This allows
      interrupts that occur simultaneously to be serviced in a prioritized
      order. Sometimes priority may be determined by frequency or rate of
      occurrence. An infrequent but lengthy interrupt service routine
      (ISR) might need to be interrupted by a more frequently occurring
      interrupt. In the following example, the ISR for INT1 temporarily
      modifies the interrupt mask register (IMR) to permit interrupt
      processing when an interrupt on INT0 (but no other) interrupt
      occurs. When the routine has finished processing, the IMR is
      restored to its original state. AR4 may substituted for AR7
      (TMS320C25) when using the TMS32020.

      .title        'INTERRUPT SERVICE ROUTINE - INT1-'
      .def   ISR1
      .ref   IMR
*
* INTERRUPT PROCESSING FOR EXTERNAL INTERRUPT INT1-
*   THIS ROUTINE MAY BE INTERRUPTED BY AN INTERRUPT FROM THE
*   EXTERNAL INTERRUPT INT0- BUT NO OTHER.
*
ISR1  LARP  AR7    ; 7 --> ARP
      MAR   *-     ;                AR7 = AR7 - 1
      SST1  *-     ; ST1  --> *AR7, AR7 = AR7 - 1
      SST   *-     ; ST0  --> *AR7, AR7 = AR7 - 1
      SACH  *-     ; ACCH --> *AR7, AR7 = AR7 - 1
      SACL  *-     ; ACCL --> *AR7, AR7 = AR7 - 1
      LDPK  0      ; DP = 0
      PSHD  IMR    ; IMR      --> TOS
      LACK  01h    ; MASK FOR INT0-
      AND   IMR    ; MASK CURRENT IMR CONTENTS
      SACL  IMR    ; ACC      --> IMR
      EINT         ; ENABLE INTERRUPTS
*
*   MAIN PROCESSING SECTION FOR ISR1
*
      DINT         ; DISABLE INTERRUPTS
      LDPK  0      ; DP = 0
      POPD  IMR    ; TOS --> IMR
      LARP  AR7    ; 7 --> ARP
      MAR   *+     ;                AR7 = AR7 + 1
      ZALS  *+     ; *AR7 --> ACCL, AR7 = AR7 + 1
      ADDH  *+     ; *AR7 --> ACCH, AR7 = AR7 + 1
      LST   *+     ; *AR7 -->  ST0, AR7 = AR7 + 1
      LST1  *+     ; *AR7 -->  ST1, AR7 = AR7 + 1
      EINT         ; ENABLE INTERRUPTS
      RET