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      The Auxiliary Register Arithmetic Unit (ARAU) allows the next
indirect address to be calculated using increment/decrement calculations
or indexed addressing in parallel to the current arithmetic operation. For
example, in the multiplication of two matrices, the operation requires
addressing across the rows (incrementing the address by one) or down the
columns (incrementing by n). The following  gives the code for multiplying
a row times a column of two 10 * 10 matrices. The first matrix resides in
RAM block B1, and the second matrix resides in block B0.

      LARK  0,>A        ; SET INDEX TO 10.
      LARP  1           ; USE AR1 FOR ADDRESSING THE COLUMN.
      LRLK  1,>300      ; POINT AR1 TO THE START OF BLOCK B1.
      CNFP              ; SET B0 TO PROGRAM ADDRESS FOR PIPELINE.
      ZAC               ; INITIALIZE THE ACCUMULATOR.
      MPYK  0           ; CLEAR THE PRODUCT REGISTER.
      RPTK  9           ; REPEAT 10 TIMES AS MATRIX DIMENSION.
      MAC   >FFOO,*0+   ; MULTIPLY ROW TIMES COLUMN.
      APAC              ; EXECUTE FINAL ACCUMULATION.
*
      This algorithm executes in 22 machine cycles. The key to this
      performance is the parallel addressing of both multiplicands
      simultaneously. The operation is made possible by the use of the
      data bus to fetch one multiplicand and the program bus to fetch the
      other. The auxiliary register indexes down the column of one matrix
      while the PC generates incremental addressing of each row of the
      other matrix. Each cycle of the repeat loop performs the following
      operations:

            1)    Accumulates the previous product,
            2)    Multiplies the row element times the column element,
            3)    Increments the row address, and
            4)    Indexes the column address.