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      Numerical analysis, floating-point computations, or other operations
      may require arithmetic to be executed with more than 32 bits of
      precision. Since the TMS320C2x are 16/32-bit fixed-point processors,
      software is required for the extended-precision of arithmetic
      operations. Subroutines that perform the extended-precision
      arithmetic functions are given. The technique consists of performing
      the arithmetic by parts, similar to the way longhand arithmetic is
      done.

      The TMS320C25 has two features that help to make extended-precision
      calculations more efficient. One of these features is the carry
      status bit. This bit is affected by all arithmetic operations of the
      accumulator (ABS, ADD, ADDC, ADDH, ADDK, ADDS, ADDT, ADLK, APAC,
      LTA, LTD, LTS, MAC, MACD, MPYA, MPYS, NEG, SBLK, SPAC, SQRA, SQRS,
      SUB, SUBB, SUBC, SUBH, SUBK, SUBS, and SUBT). The carry bit is also
      affected by the rotate and shift accumulator instructions (ROL, ROR,
      SFL, and SFR) or may be explicitly modified by the load status
      register ST1 (LST1), reset carry (RC), and set carry (SC)
      instructions. For proper operation, the overflow mode bit should be
      reset (OVM = 0) so that the accumulator results will not be loaded
      with the saturation value. Note that this means that some additional
      code may be required if overflow of the most significant portion of
      the result is expected.

      The carry bit is set whenever the addition of a value from the input
      scaling shifter or the P register to the accumulator contents
      generates a carry out of bit 31; otherwise, the carry bit is reset
      since the carry out of bit 31 is a zero. One exception to this case
      is the ADDH instruction which can only set the carry bit. This
      allows the accumulation to generate the proper single carry when
      either the addition to the lower or upper half of the accumulator
      actually causes the carry. The following help demonstrate the
      significance of the carry bit on the TMS320C25 for additions:

         C  MSB   LSB   C  MSB   LSB   C  MSB   LSB   C  MSB   LSB
         X  FFFF FFFF   X  7FFF FFFF   X  FFFF FFFF   X  7FFF FFFF
          +         1    +         1    + FFFF FFFF    + FFFF FFFF
          -----------    -----------    -----------    -----------
         1  0000 0000   0  8000 0000   1  FFFF FFFE   1  7FFF FFFE


         C  MSB   LSB   C  MSB   LSB   C  MSB   LSB   C  MSB   LSB
         X  8000 0000   X  8000 0000   1  0000 0000   1  FFFF FFFF
          +         1    + FFFF FFFF    +(ADDC)   0    +(ADDC)   0
          -----------    -----------    -----------    -----------
         0  8000 0001   1  7FFF FFFF   1  0000 0001   1  0000 0000


                C  MSB   LSB          C  MSB   LSB
                1  8000 FFFF          1  8000 FFFF
          (ADDH) + 0000 0000    (ADDH) + 7FFF 0000
                 -----------           -----------
                1  8000 FFFF          1  FFFF FFFF

      TMS320C25:

* 64-BIT ADDITION
*   TWO 64-BIT NUMBERS ARE ADDED TO EACH OTHER PRODUCING A
*   64-BIT RESULT.  THE NUMBERS X (X3,X2,X1,X0) AND Y
*   (Y3,Y2,Y1,Y0) ARE ADDED RESULTING IN W (W3,W2,W1,W0).
*
*               X3 X2 X1 X0
*             + Y3 Y2 Y1 Y0
*               -----------
*               W3 W2 W1 W0
*
ADD64   ZALH    X1       ;  ACC = X1 00
        ADDS    X0       ;  ACC = X1 X0
        ADDS    Y0       ;  ACC = X1 X0 + 00 Y0
        ADDH    Y1       ;  ACC = X1 X0 + Y1 Y0 = W1 W0
        SACL    W0
        SACH    W1
        ZALH    X3       ;  ACC = X3 00
        ADDC    X2       ;  ACC = X3 X2 + C
        ADDS    Y2       ;  ACC = X3 X2 + 00 Y2 + C
        ADDH    Y3       ;  ACC = X3 X2 + Y3 Y2 + C = W3 W2
        SACL    W2
        SACH    W3
        RET

      In a similar way to addition, the carry bit on the TMS320C25 is
      reset whenever the input scaling shifter or the P register value
      subtracted from the accumulator generates a borrow in bit 31;
      otherwise, the carry bit is set since no borrow into bit 31 is
      required. One exception is the SUBH instruction which can only reset
      the carry bit. This allows the generation of the proper single carry
      when either the subtraction from the lower or upper half of the
      accumulator actually causes the borrow. The following help
      demonstrate the significance of the carry bit on the TMS320C25 for
      subtractions:

         C  MSB   LSB   C  MSB   LSB   C  MSB   LSB   C  MSB   LSB
         X  0000 0000   X  7FFF FFFF   X  0000 0000   X  7FFF FFFF
          -         1    -         1    - FFFF FFFF    - FFFF FFFF
          -----------    -----------    -----------    -----------
         0  FFFF FFFF   1  7FFF FFFE   0  0000 0001   0  8000 0000


         C  MSB   LSB   C  MSB   LSB   C  MSB   LSB   C  MSB   LSB
         X  8000 0000   X  8000 0000   0  0000 0000   0  FFFF FFFF
          -         1    - FFFF FFFF    -(SUBB)   0    -(SUBB)   0
          -----------    -----------    -----------    -----------
         1  7FFF FFFF   0  8000 0001   0  FFFF FFFF   1  FFFF FFFE


                C  MSB   LSB          C  MSB   LSB
                0  8000 FFFF          0  8000 FFFF
          (SUBH) - 0001 0000    (SUBH) - FFFF 0000
                 -----------           -----------
                0  7FFF FFFF          0  8001 FFFF
      TMS320C25:
* 64-BIT SUBTRACTION
*   TWO 64-BIT NUMBERS ARE SUBTRACTED PRODUCING A 64-BIT
*   RESULT.  THE NUMBER Y (Y3,Y2,Y1,Y0) AND IS SUBTRACTED
*   FROM X (X3,X2,X1,X0) RESULTING IN W (W3,W2,W1,W0).
*
*               X3 X2 X1 X0
*             - Y3 Y2 Y1 Y0
*               -----------
*               W3 W2 W1 W0
*
SUB64   ZALH    X1       ;  ACC = X1 00
        ADDS    X0       ;  ACC = X1 X0
        SUBS    Y0       ;  ACC = X1 X0 - 00 Y0
        SUBH    Y1       ;  ACC = X1 X0 - Y1 Y0 = W1 W0
        SACL    W0
        SACH    W1
        ZALS    X2       ;  ACC = 00 X2
        SUBB    Y2       ;  ACC = 00 X2 - 00 Y2 - C
        ADDH    X3       ;  ACC = X3 X2 - 00 Y2 - C
        SUBH    Y3       ;  ACC = X3 X2 - Y3 Y2 - C = W3 W2
        SACL    W2
        SACH    W3
        RET

      The second feature of the TMS320C25 aiding in extended-precision
      calculations is the MPYU (unsigned multiply) instruction. The MPYU
      instruction allows two unsigned 16-bit numbers to be multiplied and
      the 32-bit result placed in the product register in a single cycle.
      Efficiency is gained by the ability to generate partial products
      from the 16-bit portions of a 32-bit or larger value instead of
      having to split the value into 15-bit or smaller parts.

      TMS320C25:

* 32 X 32-BIT MULTIPLY WITH 64-BIT RESULT
*   TWO 32-BIT NUMBERS ARE MULTIPLIED, PRODUCING A 64-BIT
*   RESULT.  THE NUMBERS X (X1,X0) AND Y (Y1,Y0) ARE
*   MULTIPLIED RESULTING IN W (W3,W2,W1,W0).
*
*                 X1 X0
*           x       Y1 Y0
*           -----------
*                 X0*Y0
*              X1*Y0
*              X0*Y1
*           X1*Y1
*           -----------
*           W3 W2 W1 W0
*
*   DETERMINE THE SIGN OF THE PRODUCT.
*
MPY32 ZALS  X1     ; ACCL = SXXX XXXX XXXX XXXX
      XOR   Y1     ; ACCL = S--- ---- ---- ----
      SACH  SIGN   ; SAVE THE PRODUCT SIGN 0=+, 1=-.
*
*   TAKE THE ABSOLUTE VALUE OF BOTH X AND Y.
*
ABSX  ZALH  X1     ; ACC = X1 00
      ADDS  X0     ; ACC = X1 X0
      ABS
      SACH  X1     ; SAVE |X1|
      SACL  X0     ; SAVE |X0|
ABSY  ZALH  Y1     ; ACC = Y1 00
      ADDS  Y0     ; ACC = Y1 Y0
      ABS
      SACH  Y1     ; SAVE |Y1|
      SACL  Y0     ; SAVE |Y0|
*
*   MULTIPLY |X| AND |Y| TO PRODUCE |W|.
*
MULT  LT    X0     ; T = X0
      MPYU  Y0     ; T = X0, P = X0*Y0
      SPL   W0     ; SAVE |W0|
      SPH   W1     ; SAVE PARTIAL |W1|
      MPYU  Y1     ; T = X0, P = X0*Y1
      LTP   X1     ; T = X1, P = X0*Y1, ACC = X0*Y1
      MPYU  Y0     ; T = X1, P = X1*Y0, ACC = X0*Y1
      ADDS  W1     ; T = X1, P = X1*Y0,
*                  ; ACC = X0*Y1 + X0*Y0*2**-16
      MPYA  Y1     ; T = X1, P = X1*Y1,
*                  ; ACC = X1*Y0 + X0*Y1 + X0*Y0*2**-16
      SACL  W1     ; SAVE |W1|
      SACH  W2     ; SAVE PARTIAL |W2|
      ZALS  W2     ; P = X1*Y1,
*                  ; ACC = (X1*Y0 + X0*Y1)*2**-16
      BNC   SUM    ; TEST FOR CARRY FROM W2
      ADDH  ONE
SUM   APAC         ; ACC = X1*Y1 + (X1*Y0+X0*Y1)*2**-16
      SACL  W2     ; SAVE |W2|
      SACH  W3     ; SAVE |W3|
*
*   TEST THE SIGN OF THE PRODUCT, NEGATE IF NEGATIVE.
*
      LAC   SIGN
      BZ    DONE   ; RETURN IF POSITIVE
*
      ZALH  W1     ; ACC = |W1 00|
      ADDS  W0     ; ACC = |W1 W0|
      CMPL
      ADD   ONE    ; ACC = W1 W0 AND CARRY GENERATION
      SACL  W0     ; SAVE W0
      SACH  W1     ; SAVE W1
      ZALS  W2     ; ACC = |00 W2|
      ADDH  W3     ; ACC = |W3 W2|
      CMPL
      ADDC  ONE    ; ACC = W3 W2
      SACL  W2     ; SAVE W2
      SACH  W3     ; SAVE W3
*
DONE  RET