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SYNTAX      [<LABEL>] SHM

OPERANDS    None

EXECUTION   (PC) + 1 . PC
            1 . HM status bit in status register ST1
            Affects HM.

DESCRIPTION The SHM instruction sets the HM status bit to logic one. In
            this mode, the TMS320C25 is halted in the normal manner
                     ____
            whenever HOLD is asserted, regardless of the PC value or the
                            __
            state of the MP/MC pin. HM may also be loaded by the LST1 and
            RHM instructions.

 WORDS       1

ENCODING    15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |1  1  0  0  1  1  1  0  0  0  1  1  1  0  0  1 |
            +-----------------------------------------------+

CYCLES

            +-----------------------------------------------+
            |     Cycle Timings for a Single Instruction    |
            |-----------------------------------------------|
            | PI/DI | PI/DE | PE/DI | PE/DE | PR/DI | PR/DE |
            |-------+-------+-------+-------+-------+-------|
      'C25  |   1   |   1   |  1+p  |  1+p  |   1   |   1   |
            |-----------------------------------------------|
            |     Cycle Timings for a Repeat Instruction    |
            |-----------------------------------------------|
      'C25  |   n   |   n   |  n+p  |  n+p  |   n   |   n   |
            +-----------------------------------------------+



EXAMPLE     SHM               HM is set, implementing the normal
                              (TMS32020-type) hold mode of operation.
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