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SYNTAX      [<LABEL>] SFSM

OPERANDS    None

EXECUTION   (PC) + 1 . PC
            1 . FSM status bit in status register ST1
            Affects FSM.

DESCRIPTION The SFSM instruction sets the FSM status bit to logic one. In
            this mode, an external FSR pulse is required for a receive
            operation, and an external FSX pulse is required if TXM = 0.
            If TXM = 1, FSX pulses are generated in the normal manner
            every time the transmit shift register XSR is loaded. See
            serial port for more information on its operation. FSM may
            also be loaded by the LST1 and RFSM instructions.


WORDS       1

ENCODING    15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |1  1  0  0  1  1  1  0  0  0  1  1  0  1  1  1 |
            +-----------------------------------------------+

CYCLES

            +-----------------------------------------------+
            |     Cycle Timings for a Single Instruction    |
            |-----------------------------------------------|
            | PI/DI | PI/DE | PE/DI | PE/DE | PR/DI | PR/DE |
            |-------+-------+-------+-------+-------+-------|
      'C25  |   1   |   1   |  1+p  |  1+p  |   1   |   1   |
            |-----------------------------------------------|
            |     Cycle Timings for a Repeat Instruction    |
            |-----------------------------------------------|
      'C25  |   n   |   n   |  n+p  |  n+p  |   n   |   n   |
            +-----------------------------------------------+



EXAMPLE     SFSM              FSM is set, putting the serial port in a
                              mode of operation where frame
                              synchronization pulses are required for each
                              word to be transmitted or received.