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SYNTAX      [<LABEL>] RFSM

OPERANDS    None

EXECUTION   (PC) + 1 . PC
            0 . FSM status bit in status register ST1
            Affects FSM.

DESCRIPTION The RFSM instruction resets the FSM status bit to logic zero.
            In this mode, external FSR pulses are not required to initiate
            the receive operation for each word received, but rather only
            one FSR pulse is required to initiate a "continuous mode" of
            operation. The same holds true for FSX when TXM = 0. After the
            first FSR/FSX pulse, these inputs are then in a "don't care"
            state. If TXM = 1, FSX is pulsed the first time DXR is loaded,
            but remains low thereafter. See "serial port" for more
            information on its operation. FSM may also be loaded by LST1
            and SFSM instructions.
WORDS       1

ENCODING    15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |1  1  0  0  1  1  1  0  0  0  1  1  0  1  1  0 |
            +-----------------------------------------------+

CYCLES

            +-----------------------------------------------+
            |     Cycle Timings for a Single Instruction    |
            |-----------------------------------------------|
            | PI/DI | PI/DE | PE/DI | PE/DE | PR/DI | PR/DE |
            |-------+-------+-------+-------+-------+-------|
      'C25  |   1   |   1   |  1+p  |  1+p  |   1   |   1   |
            |-----------------------------------------------|
            |     Cycle Timings for a Repeat Instruction    |
            |-----------------------------------------------|
      'C25  |   n   |   n   |  n+p  |  n+p  |   n   |   n   |
            +-----------------------------------------------+



EXAMPLE     RFSM              FSM is reset, putting the serial port in a
                              mode of operation where frame
                              synchronization pulses are not required.
                              This allows a continuous bit stream to be
                              transmitted/received without FSX/FSR pulses
                              every 8/16 bits.