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SYNTAX      DIRECT   [<LABEL>] MACD <dma>,<pma>
            INDIRECT [<LABEL>] MACD <pma>,{ind}[,<next ARP>]

OPERANDS    0 . pma . 65535; 0 . dma . 127; 0 . next ARP . 7.

EXECUTION   TMS32020
                  (PC) + 2 . TOS
                  pma . PC

                  If (repeat counter) is not equal to 0:
                    Then (ACC) + (shifted P register) . ACC
                      (dma) . T register
                      (dma) * (pma, addressed by PC) . P register
                      Modify AR(ARP) and ARP as specified
                      (PC) + 1 . PC
                      (repeat counter) - 1 . repeat counter
                    Else (ACC) + (shifted P register) . ACC
                      (dma) . T register
                      (dma) * (pma, addressed by PC) . P register
                      Modify AR(ARP) and ARP as specified
                  (TOS) . PC
                  Affects OV; affected by OVM and PM.
            TMS320C25
                  (PC) + 2 . PC
                  (PFC) . MCS
                  (pma) . PFC

                  If (repeat counter) is not equal to 0:
                    Then (ACC) + (shifted P register) . ACC
                      (dma) . T register
                      (dma) * (pma, addressed by PFC) . P register
                      Modify AR(ARP) and ARP as specified
                      (PFC) + 1 . PFC
                      (repeat counter) - 1 . repeat counter
                    Else (ACC) + (shifted P register) . ACC
                      (dma) . T register
                      (dma) * (pma, addressed by PFC) . P register
                      Modify AR(ARP) and ARP as specified
                  (MCS) . PFC
                  Affects C and OV; affected by OVM and PM.

DESCRIPTION The MACD instruction multiplies a data memory value (specified
            by dma) by a program memory value (specified by pma). It also
            adds the previous product, shifted as defined by the PM status
            bits, to the accumulator. The data and program memory
            locations on the TMS320C25 may be any non-reserved, on-chip
            or off-chip memory locations. If the program memory is block
            B0 of on-chip RAM, then the CNF bit must be set to one. On the
            TMS32020, data and program memory locations must reside on-
            chip. Note that on both devices, the upper eight bits of the
            program memory address should be set to >FF in order to
            address B0 program RAM, and the upper six bits of dma should
            be set to zero to address a location below 1024. When used in
            the direct addressing mode, the dma cannot be modified during
            repetition of the instruction. If MACD addresses one of the
            memory-mapped registers or external memory as a data memory
            location, the effect of the instruction will be that of a MAC
            instruction (see the DMOV instruction description).

            MACD functions in the same manner as MAC, with the addition
            of data move for block B0, B1, or B2. Otherwise, the effects
            are the same as MAC. This feature makes MACD useful for
            applications such as convolution and transversal filtering.

            When the MACD instruction is repeated, the program memory
            address contained in the PC/PFC is incremented by one during
            its operation. This enables accessing a series of operands in
            memory. When used with RPT or RPTK, MACD becomes a single-
            cycle instruction once the RPT pipeline is started.

WORDS       2

ENCODING    15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |0  1  0  1  1  1  0  0| 0| data memory address | DIRECT
            |-----------------------------------------------|
            |             program memory address            |
            +-----------------------------------------------+

            15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |0  1  0  1  1  1  0  0| 1| see indirect fields | INDIRECT
            |-----------------------------------------------|
            |             program memory address            |
            +-----------------------------------------------+

CYCLES

         +-----------------------------------------------------------+
         |           Cycle Timings for a Single Instruction          |
         |-----------------------------------------------------------|
         | PI/D |   PI/DE  |  PE/DI  |    PE/DE    | PR/DI|  PR/DE   |
         |------+----------+---------+-------------+------+----------|
    '20  |   3  |    N/A   |   3+2p  |     N/A     |   -  |    -     |
         |-----------------------------------------------------------|
    'C25 |                    Table in on-chip RAM                   |
         |-----------------------------------------------------------|
         |   3  |    4+d   |   4+2p  |    5+d+2p   |   4  |   5+d    |
         |-----------------------------------------------------------|
    'C25 |                    Table in on-chip ROM                   |
         |-----------------------------------------------------------|
         |   4  |    5+d   |   4+2p  |    5+d+2p   |   4  |   5+d    |
         |-----------------------------------------------------------|
    'C25 |                Table in external memory                   |
         |-----------------------------------------------------------|
         |  4+p |   5+d+p  |   4+3p  |    5+d+3p   |  4+p |  5+d+p   |
         |-----------------------------------------------------------|
         |           Cycle Timings for a Repeat Instruction          |
         |-----------------------------------------------------------|
         | PI/D |   PI/DE  |  PE/DI  |    PE/DE    | PR/DI|  PR/DE   |
         |------+----------+---------+-------------+------+----------|
    '20  |  2+n |    N/A   | 2+n+2p  |     N/A     |   -  |    -     |
         |-----------------------------------------------------------|
    'C25 |                    Table in on-chip RAM                   |
         |-----------------------------------------------------------|
         |  2+n |  2+2n+nd | 3+n+2p  | 3+2n+nd+2p  |  3+n | 3+2n+nd  |
         |-----------------------------------------------------------|
    'C25 |                    Table in on-chip ROM                   |
         |-----------------------------------------------------------|
         |  3+n |  3+2n+nd | 3+n+2p  | 3+2n+nd+2p  |  3+n | 3+2n+nd  |
         |-----------------------------------------------------------|
    'C25 |                  Table in external memory                 |
         |-----------------------------------------------------------|
         |3+n+np|3+2n+nd+np|3+n+np+2p|3+2n+nd+np+2p|3+n+np|3+2n+nd+np|
         +-----------------------------------------------------------+



EXAMPLE     SPM   0           Select no shift mode on PR output
            SOVM              Set overflow mode
            CNFP              Configure block B0 as program memory (>FFXX)
            LARP  3           Use AR3 to address block B1
            LRLK  3,1023      Point to highest location in RAM block B1
            RPTK  255         Compute 1 sample of length 256 convolution
            MACD >FF00,*-     Multiply/accumulate, shift data word in
                              block B1, and decrement AR3

                      BEFORE                    AFTER

                AR3     >3FD            AR3      >3FC
                RPT      >FD            RPT       >FC
             PC/PFC    >FF02         PC/PFC     >FF03
             dm1021      >23         dm1021       >23
             dm1022     >7FC         dm1022       >23
            pm65282    >FAAA        pm65282     >FAAA
                  P  >458972              P >FFFF453E
              ACC X >723EC41          ACC 0  >76975B3
                  C                       C

            Note: The data move function for MACD can only occur within
                  on-chip data RAM blocks B0, B1, and B2.