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SYNTAX      DIRECT   [<LABEL>] MAC <dma>,<pma>
            INDIRECT [<LABEL>] MAC <pma>,{ind}[,<next ARP>]

OPERANDS    0 . pma . 65535; 0 . dma . 127; 0 . next ARP . 7.

EXECUTION   TMS32020
                  (PC) + 2 . TOS
                  pma . PC

                  If (repeat counter) is not equal to 0:
                    Then (ACC) + (shifted P register) . ACC
                      (dma) . T register
                      (dma) * (pma, addressed by PC) . P register
                      Modify AR(ARP) and ARP as specified
                      (PC) + 1 . PC
                      (repeat counter) - 1 . repeat counter
                    Else (ACC) + (shifted P register) . ACC
                      (dma) . T register
                      (dma) * (pma, addressed by PC) . P register
                      Modify AR(ARP) and ARP as specified
                  (TOS) . PC
                  Affects OV; affected by OVM and PM.

            TMS320C25
                  (PC) + 2 . PC
                  (PFC) . MCS
                  (pma) . PFC

                  If (repeat counter) is not equal to 0:
                    Then (ACC) + (shifted P register) . ACC
                      (dma) . T register
                      (dma) * (pma, addressed by PFC) . P register
                      Modify AR(ARP) and ARP as specified
                      (PFC) + 1 . PFC
                      (repeat counter) - 1 . repeat counter
                    Else (ACC) + (shifted P register) . ACC
                      (dma) . T register
                      (dma) * (pma, addressed by PFC) . P register
                      Modify AR(ARP) and ARP as specified
                  (MCS) . PFC
                  Affects C and OV; affected by OVM and PM.

DESCRIPTION The MAC instruction multiplies a data memory value (specified
            by dma) by a program memory value (specified by pma). It also
            adds the previous product, shifted as defined by the PM status
            bits, to the accumulator. The data and program memory
            locations on the TMS320C25 may be any non-reserved, on-chip
            or off-chip memory locations. If the program memory is block
            B0 of on-chip RAM, then the CNF bit must be set to one. On the
            TMS32020, data and program memory locations must reside on-
            chip. Note that on both devices, the upper eight bits of the
            program memory address should be set to >FF in order to
            address B0 program RAM, and the upper six bits of dma should
            be set to zero to address a location below 1024. When used in
            the direct addressing mode, the dma cannot be modified during
            repetition of the instruction.

            When the MAC instruction is repeated, the program memory
            address contained in the PC/PFC is incremented by one during
            its operation. This enables accessing a series of operands in
            memory. MAC is useful for long sum-of-products operations,
            since MAC becomes a single-cycle instruction once the RPT
            pipeline is started.

WORDS       2

ENCODING    15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |0  1  0  1  1  1  0  1| 0| data memory address | DIRECT
            |-----------------------------------------------|
            |             program memory address            |
            +-----------------------------------------------+

            15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |0  1  0  1  1  1  0  1| 1| see indirect fields | INDIRECT
            |-----------------------------------------------|
            |             program memory address            |
            +-----------------------------------------------+

CYCLES

         +-----------------------------------------------------------+
         |           Cycle Timings for a Single Instruction          |
         |-----------------------------------------------------------|
         | PI/D |   PI/DE  |  PE/DI  |    PE/DE    | PR/DI|  PR/DE   |
         |------+----------+---------+-------------+------+----------|
    '20  |   3  |    N/A   |   3+2p  |     N/A     |   -  |    -     |
         |-----------------------------------------------------------|
    'C25 |                    Table in on-chip RAM                   |
         |-----------------------------------------------------------|
         |   3  |    4+d   |   4+2p  |    5+d+2p   |   4  |   5+d    |
         |-----------------------------------------------------------|
    'C25 |                    Table in on-chip ROM                   |
         |-----------------------------------------------------------|
         |   4  |    5+d   |   4+2p  |    5+d+2p   |   4  |   5+d    |
         |-----------------------------------------------------------|
    'C25 |                Table in external memory                   |
         |-----------------------------------------------------------|
         |  4+p |   5+d+p  |   4+3p  |    5+d+3p   |  4+p |  5+d+p   |
         |-----------------------------------------------------------|
         |           Cycle Timings for a Repeat Instruction          |
         |-----------------------------------------------------------|
         | PI/D |   PI/DE  |  PE/DI  |    PE/DE    | PR/DI|  PR/DE   |
         |------+----------+---------+-------------+------+----------|
    '20  |  2+n |    N/A   | 2+n+2p  |     N/A     |   -  |    -     |
         |-----------------------------------------------------------|
    'C25 |                    Table in on-chip RAM                   |
         |-----------------------------------------------------------|
         |  2+n |  2+2n+nd | 3+n+2p  | 3+2n+nd+2p  |  3+n | 3+2n+nd  |
         |-----------------------------------------------------------|
    'C25 |                    Table in on-chip ROM                   |
         |-----------------------------------------------------------|
         |  3+n |  3+2n+nd | 3+n+2p  | 3+2n+nd+2p  |  3+n | 3+2n+nd  |
         |-----------------------------------------------------------|
    'C25 |                  Table in external memory                 |
         |-----------------------------------------------------------|
         |3+n+np|3+2n+nd+np|3+n+np+2p|3+2n+nd+np+2p|3+n+np|3+2n+nd+np|
         +-----------------------------------------------------------+



EXAMPLE     SPM   3           Select a shift-right-by-6 mode on PR output
            CNFP              Configure block B0 as program memory (>FFXX)
            LARP  1           Use AR1 to address block B1
            LRLK  1,768       Point to lowest location in RAM block B1
            RPTK  255         Compute 256 sum-of-product operations
            MAC  >FF00,*+     Multiply/accumulate and increment AR1

                      BEFORE                    AFTER

                AR1     >302            AR1      >303
                RPT      >FD            RPT       >FC
             PC/PFC    >FF02         PC/PFC     >FF03
              dm770      >23          dm770       >23
            pm65282    >FAAA        pm65282     >FAAA
                  P   458972              P >FFFF453E
              ACC X >723EC41          ACC 0  >7250266
                  C                       C