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CMOVcc          Conditional Move                     Flags: Not altered

CMOVcc destination, source                           CPU: PPro+

        Logic   if condition
                   destination . source
                endif

    Conditional moves test the flags which have been set by a previous
    instruction. If the given condition is true, the source operand is
    transferred (copied) into the destination operand.

    These instructions can move a 16- or 32-bit value from memory to a
    general-purpose register or from one general-purpose register to
    another. Conditional moves of 8-bit register operands are not
    supported.


        Note
        The CMOVcc instructions are new for the Pentium Pro
        processor family; however, they may not be supported
        by all the processors in the family. By checking the
        processor's feature information with CPUID, a program
        can determine if the CPU supports CMOVcc.


    A condition code (cc) is associated with each instruction to
    indicate the condition being tested for. The terms "above" and
    "below" are used for un-signed integers; "less" and "greater" for
    signed integers.
    Note that several mnemonics have the same meaning.


    Instruction         Move if ...                    Flags
    CMOVA,  CMOVNBE     Above, Not Below or Equal      CF=0 AND ZF=0
    CMOVAE, CMOVNB,     Above or Equal, Not Below,
      CMOVNC              Not Carry                    CF=0
    CMOVBE, CMOVNA      Below or Equal, Not Above      CF=1 OR ZF=1
    CMOVB,  CMOVC,      Below, Carry,
      CMOVNAE             Not Above or Equal           CF=1
    CMOVE,  CMOVZ       Equal, Zero                    ZF=1
    CMOVNE, CMOVNZ      Not Equal, Not Zero            ZF=0
    CMOVP,  CMOVPE      Parity, Parity Even            PF=1
    CMOVNP, CMOVPO      No Parity, Parity Odd          PF=0

    CMOVG,  CMOVNLE     Greater, Not Less or Equal     SF=OF AND ZF=0
    CMOVGE, CMOVNL      Greater or Equal, Not Less     SF=OF
    CMOVLE, CMOVNG      Less or Equal, Not Greater     SF<>OF OR ZF=1
    CMOVL,  CMOVNGE     Less, Not Greater or Equal     SF<>OF
    CMOVO               Overflow                       OF=1
    CMOVNO              No Overflow                    OF=0
    CMOVS               Sign (negative)                SF=1
    CMOVNS              No Sign (positive)             SF=0


    Opcode      Format
    0F 40 cw    CMOVO  r16, r/m16
    0F 40 cd    CMOVO  r32, r/m32
    0F 41 cw    CMOVNO r16, r/m16
    0F 41 cd    CMOVNO r32, r/m32
    0F 42 cw    CMOVB  r16, r/m16
    0F 42 cd    CMOVB  r32, r/m32
    0F 43 cw    CMOVAE r16, r/m16
    0F 43 cd    CMOVAE r32, r/m32
    0F 44 cw    CMOVE  r16, r/m16
    0F 44 cd    CMOVE  r32, r/m32
    0F 45 cw    CMOVNE r16, r/m16
    0F 45 cd    CMOVNE r32, r/m32
    0F 46 cw    CMOVBE r16, r/m16
    0F 46 cd    CMOVBE r32, r/m32
    0F 47 cw    CMOVA  r16, r/m16
    0F 47 cd    CMOVA  r32, r/m32
    0F 48 cw    CMOVS  r16, r/m16
    0F 48 cd    CMOVS  r32, r/m32
    0F 49 cw    CMOVNS r16, r/m16
    0F 49 cd    CMOVNS r32, r/m32
    0F 4A cw    CMOVP  r16, r/m16
    0F 4A cd    CMOVP  r32, r/m32
    0F 4B cw    CMOVNP r16, r/m16
    0F 4B cd    CMOVNP r32, r/m32
    0F 4C cw    CMOVL  r16, r/m16
    0F 4C cd    CMOVL  r32, r/m32
    0F 4D cw    CMOVGE r16, r/m16
    0F 4D cd    CMOVGE r32, r/m32
    0F 4E cw    CMOVLE r16, r/m16
    0F 4E cd    CMOVLE r32, r/m32
    0F 4F cw    CMOVG  r16, r/m16
    0F 4F cd    CMOVG  r32, r/m32


    Length and timing
    Operands    Bytes   8088    186     286     386     486     Pentium  PPro
    reg, reg      3      -       -       -       -       -       -        ??
    reg, mem   3+d(0-2)  -       -       -       -       -       -        ??