Click above to get retro games delivered to your door ever month!

CPUID           Identify CPU                         Flags: Not altered

CPUID                                                CPU: Pentium+ (*)

        Logic   case EAX of
                   0 : EAX . Highest input value recognized by CPUID
                       EBX:ECX:EDX . Vendor ID string
                   1 : EAX . CPU stepping ID, model, family, type
                       EBX:ECX . Reserved
                       EDX . Feature flags
                   2 : EAX:EBX:ECX:EDX . Cache information
                otherwise
                   EAX:EBX:ECX:EDX . Undefined
                endcase

    CPUID identifies CPU and revision information for the installed CPU.
    The instruction (currently) has 3 functions, all expecting input in
    EAX and all returning information in the EAX, EBX, ECX, and EDX
    registers.

    i)  Entry:  EAX = 0  Check CPU installed
        Return: EAX = Max. value of EAX before executing CPUID
                      (max. function number supported)
                EBX:EDX:ECX = 12-byte vendor ID string,
                      e.g. "GenuineIntel":
                      EBX = 756e6547h  ; "uneG"
                      EDX = 49656e69h  ; "Ieni"
                      ECX = 6c65746eh  ; "letn"

    ii) Entry:  EAX = 1  Get model-specific information
        Return: EAX bits 0-3   Stepping level  (e.g. 5 on 486DX-2/66)
                    bits 4-7   Model  (e.g. 3 on 486DX-2/66)
                    bits 8-11  Family (4=80486, 5=Pentium, 6=P6)
                    bits 12-31 Reserved (zero)
                EBX bits 0-31  Reserved (zero)
                ECX bits 0-31  Reserved (zero)
                EDX Feature flags (1 means option available):
                    bit        feature
                     0  FPU    On-chip FPU, executes i387 instructions
                     1  VME    Virtual 8086 Mode Enhancements supported:
                               - CR4.VME bit enables V86 mode extensions
                               - CR4.PVI bit enables protected-mode
                                 virtual interrupts
                               - Expansion of the TSS with the software
                                 indirection bitmap
                               - EFLAGS.VIF bit enables the virtual
                                 interrupt flag.
                               - EFLAGS.VIP bit enables the virtual
                                 interrupt pending flag.
                     2  DE     I/O breakpoints possible
                     3  PSE    4 MB paging supported
                     4  TSC    RDTSC instruction supported
                     5  MSR    Has Pentium-compatible Model Specific
                                 Registers
                     6  PAE    Physical Address Extension > 32 bits
                     7  MCE    Machine Check Exception supported
                     8  CX8    CMPXCHG8B instruction supported
                     9  APIC   On-chip Advanced Programmable Interrupt
                               Controller exists, is enabled, and
                               available for use.
                    10         Reserved
                    11         Reserved
                    12  MTRR   Memory Type Range Registers supported
                    13  PGE    PTE Global Flag. Processor supports the
                               CR4.PGE flag enabling the global bit in
                               both PTDEs and PTEs.
                    14  MCA    Machine Check Architecture. Processor
                               supports the MCG_CAP (machine check
                               global capability) MSR.
                    15  CMOV   CMOVcc instructions supported.
                               The FCMOVcc and FCOMI instructions are
                               supported if bit 0 (FPU) is also set.
                    16-31      Reserved (zero)
                    Assume zero if bit is not mentioned.

    iii) Entry: EAX = 2  Get cache information (Pentium Pro+)
        Return: EAX bits 0-7   Number of times the CPUID instruction
                               must be executed with an input value of 2
                               (two) to get a complete description of
                               the processor's caches and TLBs.
                               Pentium Pro will return 1.
                    bits 8-30  Cache information. Refer to Intel doc.
                    bit  31    0 = Register has valid information
                               1 = Reserved
                EBX bits 0-30  Cache information. Refer to Intel doc.
                    bit  31    0 = Register has valid information
                               1 = Reserved
                ECX bits 0-30  Cache information. Refer to Intel doc.
                    bit  31    0 = Register has valid information
                               1 = Reserved
                EDX bits 0-30  Cache information. Refer to Intel doc.
                    bit  31    0 = Register has valid information
                               1 = Reserved


    Note
    The CPUID instruction was introduced with the Pentium processor but
    works on later Intel 80486 models, too.
    The ID flag in the EFLAGS register can be used to determine if this
    instruction is supported. If a procedure is able to set or clear
    this flag, the CPUID is supported by the processor running the
    procedure.

    Executing CPUID on an early 80486 produces an invalid opcode
    exception.


    Opcode      Format
    0F A2       CPUID


    Length and timing
    Operands    Bytes   8088    186     286     386     486     Pentium
    -             2     -       -       -       -       -       14   NP