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PSRAW           Packed Shift Right Arithmetic, Word

PSRAW destination, count                             CPU: MMX

        Logic   mm(15..0)  <- SignExtend (mm(15..0)  SAR count)
                mm(31..16) <- SignExtend (mm(31..16) SAR count)
                mm(47..32) <- SignExtend (mm(47..32) SAR count)
                mm(63..48) <- SignExtend (mm(63..48) SAR count)

    PSRAW performs a shift-arithmetic-right (SAR) operation on each of
    the four words in the destination operand. The count operand
    determines the number of bits to right-shift. The new high-order
    bits of each word are filled with the initial value of the sign bit
    of the word.
    If the value specified by count is greater than 15 (0Fh), each word
    is filled with the initial value of its sign bit.

    The destination operand is an MMX register. The count operand (source
    operand) can be either an MMX register, a 64-bit memory operand, or
    an immediate 8-bit operand. 


    Opcode      Format
    0F E1 /r    PSRAW mm, mm/m64
    0F 71 /4 ib PSRAW mm, imm8