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PSLLD           Packed Shift Left Logical, Doubleword

PSLLD destination, count                             CPU: MMX

        Logic   mm(31..0)  <- mm(31..0)  SHL count
                mm(63..32) <- mm(63..32) SHL count

    PSLLD shifts the bits of the first operand to the left by the amount
    of bits specified in the count operand and returns the result to the
    destination register. The empty low-order bits are cleared (set to
    zero).
    If the value specified by the count operand is greater than 31 (1Fh)
    the destination is set to all zeros.

    The destination operand is an MMX register. The count operand (source
    operand) can be either an MMX register, a 64-bit memory operand, or
    an immediate 8-bit operand.


    Opcode      Format
    0F F2 /r    PSLLD mm, mm/m64
    0F 72 /6 ib PSLLD mm, imm8