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    The MMX technology is an extension to the Intel Architechture (IA)
    instruction set. MMX adds 57 new opcodes, a new 64-bit quadword data
    type, and eight directly adressable 64-bit registers.


        MMX register set

         1 0      63                                     0
        +---+    +----------------------------------------+ MM7
        |---|    |----------------------------------------| MM6
        |---|    |----------------------------------------| MM5
        |---|    |----------------------------------------| MM4
        |---|    |----------------------------------------| MM3
        |---|    |----------------------------------------| MM2
        |---|    |----------------------------------------| MM1
        |---|    |----------------------------------------| MM0
        +---+    +----------------------------------------+
         Tag      MMX register
        field


        Packed data types

        Packed byte: 8 bytes packed into 64 bits:
        63                            32 31           16 15    8 7     0
        +---------------------------------------------------------------+
        |       |       |       |       |       |       |       |       |
        +---------------------------------------------------------------+

        Packed word: 4 words packed into 64 bits:
        63                            32 31           16 15            0
        +---------------------------------------------------------------+
        |               |               |               |               |
        +---------------------------------------------------------------+

        Packed doubleword: 2 doublewords packed into 64 bits:
        63                            32 31                            0
        +---------------------------------------------------------------+
        |                               |                               |
        +---------------------------------------------------------------+
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