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Addressing modes


    8086+

    Base        Index      Displacement
    BX or BP    SI or DI   16-bit immediate

    Default segment is DS; SS if BP is base register.



    80386+ (32-bit addressing only)

    Base                    Index                   Displacement
    EAX,ECX,EDX,EBX,        EAX,ECX,EDX,EBX,        32-bit immediate
    ESP,EBP,ESI, or EDI     EBP,ESI, or EDI
                            scaled by 1,2,4, or 8

    Default segment is DS; SS if EBP or ESP is base register.



    Some instructions access memory to fetch or store data; other
    instructions use memory-references to locate the target of a jump
    or procedure call. In either case, the instruction must specify
    the address of the memory location being referenced. The part of
    the instruction that provides the memory location is called the
    address field. The contents of the address field is the stated
    address, and the address of the referenced memory location is
    the effective address.


    Operand-size attribute and address-size attribute

    All instructions operate on either 0, 1, 2, or 3 operands. On the
    80386+, operands can be 8, 16, or 32 bits long. When executing
    16-bit code, they are 8 or 16 bits (operand-size attribute 16
    bits); when executing 32-bit code, they are 8 or 32 bits
    (operand-size attribute 32 bits). Prefixes can be added to
    operands to override the default lengths, i.e. use 32-bit operands
    for 16-bit code and vice versa.

    Memory is accessed with either 16- or 32-bit addresses. Each
    instruction that accesses memory has an address-size attribute of
    16 or 32 bits. A 16-bit address both indicates the use of a 16-bit
    displacement in the instruction and an effective address
    calculation; in other words, it means the generation of a 16-bit
    address offset (a segment-relative address). The 32-bit addresses
    use a 32-bit displacement and the generation of a 32-bit address
    offset. Any instruction that reads or writes a 16-bit word or a
    32-bit doubleword has an operand-size attribute of either 16 or 32
    bits.

    Instructions that implicitly use a stack, such as PUSH EAX, also
    have a stack address-size attribute of either 16 or 32 bits. To
    form the address of the top of the stack, the 16-bit addresses use
    the 16-bit SP register. Instructions with a stack address-size
    attribute of 32 bits use the 32-bit ESP register. The stack
    address size attribute is shown by the "D-bit" (B-bit) in the SS
    segment descriptor. If D=0, the stack address-size attribute is 16
    bits; if D=1, the attribute is 32 bits.

    
    In protected mode, the processor determines the default operand
    size of the instruction it is executing by examining the "D-bit"
    in the CS segment descriptor. If D=0, all operand lengths and
    effective addresses are assumed to be 16 bits long. If D=1, the
    operands and addresses are 32 bits long.
    In real mode and in virtual 8086 mode, the default operand and
    address size is 16 bits (no descriptors in real mode).

    Regardless of default size, two prefixes (the operand-size prefix
    (66h), and the address-size prefix (67h)) override the D-bit value
    on an individual instruction basis. These prefixes are automatically
    added by assemblers that support the 80386 processor.

    
        Examples

        ideal
        p386n
        ; Instruction   Object code generated if ...
        ;               segment _TEXT use16     segment _TEXT use32
        mov  al,[bx]    ; 8A 07                 ; 67 8A 07
        mov  ax,[bx]    ; 8B 07                 ; 66 67 8B 07
        mov  eax,[bx]   ; 66 8B 07              ; 67 8B 07
        mov  al,[ebx]   ; 67 8A 03              ; 8A 03
        mov  ax,[ebx]   ; 67 8B 03              ; 66 8B 03
        mov  eax,[ebx]  ; 66 67 8B 03           ; 8B 03
        push ax         ; 50                    ; 66 50
        push eax        ; 66 50                 ; 50
        pop  edx        ; 66 5A                 ; 5A
        pop  dx         ; 5A                    ; 66 5A
        ; ...
                        ends                    ends