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System address registers (80286+)
(a.k.a. Segmented memory management registers)

    Four registers locate the data structures that control segmented
    memory management. These registers are defined to reference the
    tables or segments supported by the 80286/80386/80486/Pentium
    protection model.
    The addresses of these tables and segments are stored in special
    System Address and System Segment Registers.

    GDTR - Global Descriptor Table Register
           Holds the 32-bit linear base address and the 16-bit limit
           of the Global Descriptor Table.

    LDTR - Local Descriptor Table Register
           Holds the 16-bit selector for the Local Descriptor Table.
           Because the LDT is a task-specific segment, it is defined
           by selector values stored in the system segment registers.
           There is a programmer-invisible segment descriptor register
           associated with the LDT.

    IDTR - Interrupt Descriptor Table Register
           This register points to a table of entry points for
           interrupt handlers (the IDT). The register holds the 32-bit
           linear base address and the 16-bit limit of the Interrupt
           Descriptor Table.

    TR   - Task Register
           This register points to the information needed by the
           processor to define the current task. The register holds
           the 16-bit selector for the Task State Segment descriptor.
           Because the TSS segment is task-specific, it is defined by
           selector values stored in the system segment registers.