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RDPMC           Read Performance-Monitoring Counters Flags: Not altered

RDPMC                                                CPU: PPro+ r

        Logic   if (ECX < 2) and
                   ((CR4.PCE = 1) or ((CR4.PCE = 0) and (CPL=0)))
                   EDX:EAX . PMC[ECX]
                else
                   #GP(0)
                endif

    Loads the contents of the 40-bit performance-monitoring counter
    specified in the ECX register into registers EDX:EAX. The EDX
    register is loaded with the high-order 8 bits of the counter and the
    EAX register is loaded with the low-order 32 bits. The Pentium Pro
    processor has two performance-monitoring counters (0 and 1), which
    are specified by placing 0000H or 0001H, respectively, in the ECX
    register.

    The RDPMC instruction allows application code running at a privilege
    level of 1, 2, or 3 to read the performance-monitoring counters if
    the PCE flag in the CR4 register is set. This instruction is
    provided to allow performance monitoring by application code without
    incurring the overhead of a call to an operating-system procedure.

    The performance-monitoring counters are event counters that can be
    programmed to count events such as the number of instructions
    decoded, number of interrupts received, or number of cache loads.
    Appendix B, Performance Monitoring Counters, in the Pentium Pro
    Family Developer's Manual, Volume 3 lists all the events that can be
    counted.

    The RDPMC instruction does not serialize instruction execution. That
    is, it does not imply that all the events caused by the preceding
    instructions have been completed or that events caused by subsequent
    instructions have not begun. If an exact event count is desired,
    software must use a serializing instruction (such as the CPUID
    instruction) before and/or after the execution of the RDPCM
    instruction.

    The RDPMC instruction can execute in 16-bit addressing mode or
    virtual 8086 mode; however, the full contents of the ECX register
    are used to determine the counter to access and a full 40-bit result
    is returned (the low-order 32 bits in the EAX register and the
    high-order 9 bits in the EDX register).


    Note
    According to Intel's Pentium Pro manual, "this instruction was
    available in the Pentium processor, but was undocumented".


    Protected Mode Exceptions
    #GP(0) If the current privilege level is not 0 and the PCE flag in the
    CR4 register is clear.
    If the value in the ECX register is not 0 or 1.

    Real Address Mode Exceptions
    #GP If the PCE flag in the CR4 register is clear.
    If the value in the ECX register is not 0 or 1.

    Virtual 8086 Mode Exceptions
    #GP(0) If the PCE flag in the CR4 register is clear.
    If the value in the ECX register is not 0 or 1.


    Opcode      Format
    0F 33       RDPMC


    Length and timing
    Operands    Bytes   8088    186     286     386     486     Pentium
    -           2       -       -       -       -       -       -