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SYNTAX      DIRECT   [<LABEL>] BIT <dma>,<bit code>
            INDIRECT [<LABEL>] BIT {ind},<bit code>[,<next ARP>]

OPERANDS    0 . dma . 127; 0 . next ARP . 7; 0 . bit code . 15.

EXECUTION   (PC) + 1 . PC
            (dma bit at bit address (15-bit code)) . TC.
            Affects TC (see note after example).

DESCRIPTION The BIT instruction copies the specified bit of the data
            memory value to the TC bit of status register ST1. Note that
            the BITT, CMPR, LST1, and NORM instructions also affect the
            TC bit in status register ST1. A bit code value is specified
            that corresponds to a certain bit address in the instruction
            as given by the following table:

            BIT ADDRESS      BIT CODE        BIT ADDRESS       BIT CODE
            (LSB)  (MSB)   11 10  9  8      (LSB)  (MSB)     11 10  9  8
                 0          1  1  1  1            8           0  1  1  1
                 1          1  1  1  0            9           0  1  1  0
                 2          1  1  0  1           10           0  1  0  1
                 3          1  1  0  0           11           0  1  0  0
                 4          1  0  1  1           12           0  0  1  1
                 5          1  0  1  0           13           0  0  1  0
                 6          1  0  0  1           14           0  0  0  1
                 7          1  0  0  0           15           0  0  0  0
            The bit code for bit address X is bit complement X.

WORDS       1

ENCODING    15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |1  0  0  1|  bit code | 0| data memory address | DIRECT
            +-----------------------------------------------+

            15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |1  0  0  1|  bit code | 1| see indirect fields | INDIRECT
            +-----------------------------------------------+

CYCLES

            +------------------------------------------------+
            |    Cycle Timings for a Single Instruction      |
            |------------------------------------------------|
            | PI/DI | PI/DE | PE/DI | PE/DE  | PR/DI | PR/DE |
            |-------+-------+-------+--------+-------+-------|
      '20   |   1   |  2+d  |  1+p  | 2+d+p  |   -   |   -   |
            |-------+-------+-------+--------+-------+-------|
     'C25   |   1   |  2+d  |  1+p  | 2+d+p  |   1   |  2+d  |
            |------------------------------------------------|
            |    Cycle Timings for a Repeat Instruction      |
            |------------------------------------------------|
      '20   |   n   | 2n+nd |  n+p  |2n+nd+p |   -   |   -   |
            |-------+-------+-------+--------+-------+-------|
     'C25   |   n   | 1+n+nd|  n+p  |1+n+nd+p|   n   |1+n+nd |
            +------------------------------------------------+



EXAMPLE     BIT   >0,>8       (DP = 488)
            or
            BIT   *,8         If the current auxiliary register contains
                              >F400

                    BEFORE              AFTER

              dmF400 >7E98       dmF400 >FE98
                  TC    >0           TC    >1

NOTE        This instruction may affect the contents of the accumulator
            on the TMS32020 if the following conditions occur:
                  1) Overflow mode set (OVM status register is set);
                  2) Two LSB's of BIT opcode (bits 8 and 9 of the
                  instruction word) are zero;
                  3) Addition of the accumulator contents with the
                  contents of the addressed memory would cause accumulator
                  overflow.
            If all of the above conditions are met, the contents of the
            accumulator will be replaced by the positive or negative
            saturation value, depending upon the polarity of the overflow.

            This situation may be avoided by any one of the following
            means:
                  1) Precede BIT instruction with ROVM, and follow BIT
                  with SOVM instruction.
                  2) If direct addressing is being used, reorganize memory
                  so that page relative locations 0, 4, 8, C, and 10 are
                  not used.
                  3) If indirect addressing is used, select new ARP that
                  is not AR0 or AR4 and restore code later (if necessary)
                  with LARP AR0/4.
                  4) Use BITT instead of BIT. BITT does not affect
                  accumulator under any circumstances.
                  5) Use TMS320C25 (pin and object code compatible)
                  instead.

            This situation occurs only when the BIT instruction is
            executed by a TMS32020 that is in the saturation mode.