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      A full-duplex on-chip serial port provides direct communication with
      serial devices such as codecs, serial A/D converters, and other
      serial systems. The interface signals are compatible with codecs and
      many other serial devices with minimum external hardware. The serial
      port may also be used for intercommunication between processors in
      multi-processing applications.

      Both receive and transmit operations are double-buffered on the
      TMS320C25, thus allowing a continuous bit stream even if FSX is an
      output. The use of the frame sync mode (FSM) bit provides continuous
      operation that once initiated requires no further frame
      synchronization pulses. No minimum CLKR/CLKX frequency (f(min) = 0
      Hz) is required for serial port operation.

          Serial Port Bits/Pins/Registers          TMS32020    TMS320C25

      FO    Format Bit                                Yes         Yes
      TXM   Transmit mode bit                         Yes         Yes
      FSM   Frame synchronization mode bit            No          Yes
      CLKX  Transmit clock signal                     Yes         Yes
      CLKR  Receive clock signal                      Yes         Yes
      DX    Transmitted serial data signal            Yes         Yes
      DR    Received serial data signal               Yes         Yes
      FSX   Transmit framing synchronization signal   Yes         Yes
      FSR   Receive framing synchronization signal    Yes         Yes
      DXR   Data transmit register                    Yes         Yes
      DRR   Data receive register                     Yes         Yes
      XSR   Transmit shift register                   No          Yes
      RSR   Receive shift register                    No          Yes

      The serial port uses two memory-mapped registers: the data transmit
      register (DXR) that holds the data to be transmitted by the serial
      port, and the data receive register (DRR) that holds the received
      data. Both registers operate in either the 8-bit byte mode or 16-
      bit word mode, and may be accessed in the same manner as any other

                  address     MSB              LSB
                              +-------------------+
                   >0000      |        DRR        |
                              +-------------------+
                              +-------------------+
                   >0001      |        DXR        |
                              +-------------------+

      data memory location. Each register has an external, a framing
      synchronization pulse, and associated shift registers. Any
      instruction accessing data memory can be used to read from or write
      to these registers; however the BLKD (block move from data memory
      to data memory) instruction cannot be used to read these registers.
      The DXR and DRR registers are mapped into locations 0 and 1 in the
      data address space. The XSR and RSR registers are not directly
      accessible through software.

      If the serial port is not being used, the DXR and DRR registers can
      be used as general-purpose registers. In this case, the CLKR and FSR
      should be connected to logic low to prevent a possible receive
      operation from being initiated.

      Three bits in status register ST1 are used to control the serial
      port operation: FO, TXM, and FSM. The FO (format) bit defines
      whether the data to be transmitted and received is an 8-bit byte or
      a 16-bit word. If FO = 0, the data is formatted in 16-bit words. If
      FO = 1, the data is transmitted in 8-bit bytes. In the 8-bit mode,
      only the eight least-significant bits are used for transmit/receive
      operations. The FO bit is loaded by the FORT (format serial port
      registers) instruction. On reset, FO is set to zero.

      The TXM (transmit mode) bit is used to determine if the frame
      synchronization pulse for the transmit operation is generated
      externally or internally. If TXM = 1, the FSX pin becomes an output
      pin, and a framing pulse is produced on the FSX pin every time the
      DXR register is loaded. This framing pulse is synchronized with the
      rising edge of CLKX. If TXM = 0, the FSX pin an input pin. The
      TMS320C2x then waits for an external synchronization pulse before
      beginning transmission. On a reset, TXM is set to zero, configuring
      FSX to be an input. The TXM bit can be loaded by the LST1, STXM, or
      RTXM instructions. If DXR on the TMS32020 is loaded before the
      previous word is completely sent, the serial port immediately begins
      transmitting the new word. The bits of the previous word that have
      not been sent are lost. If TXM = 1 on the TMS32020, a new FSX pulse
      is generated. If TXM = 0, the serial port immediately begins
      transmitting the new word without waiting for a new external FSX
      pulse.

      The FSM (frame synchronization pulse) status register bit is used
      to select whether frame sync pulses are required for each serial
      port transfer. If FSM = 1, frame sync pulses are required; if FSM
      = 0, they are not required. FSM is set by the SFSM (set frame
      synchronization mode) instruction and cleared by the RFSM (reset
      frame synchronization mode) instruction. When FSM = 1 and frame sync
      pulses are required, an FSX pulse will cause the XSR to be loaded
      with data from the DXR, and transmission will begin. If an FSX is
      presented prior to the last bit of the current transmission, the XSR
      will be reloaded from the DXR, thus aborting the current
      transmission and immediately beginning a new one.

      The frame sync mode is useful in communicating to "PCM highways".
      For ATT T1 and CCITT G711/712 lines, the processor can communicate
      directly in these formats by counting the transmitted/received bytes
      in software and performing SFSM/RFSM instructions as needed to
      set/reset the FSM bit. See the Second Generation User's Guide for
      more detailed information on the serial port.