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      Reset is a non-maskable external interrupt that can be used at any
      time to put the TMS320C2x into a known state. Reset is typically
      applied after powerup when the machine is in a random state.
                  __
      Driving the RS signal low causes the TMS320C2x to terminate
      execution and forces the program counter to zero. Reset affects
      various registers and status bits. At powerup, the state of the
      processor is undefined. For correct system operation after powerup,
      a reset signal must be asserted low for at least three clock cycles
      to guarantee  a reset of the device. Processor execution begins at
      location 0, which normally contains a B (branch) statement to direct
      program execution to the system initialization routine.
                        __
      Upon receiving an RS signal, the following actions take place:

      1)    A logic 0 is loaded into the CNF (configuration control) bit
            in status register ST1, causing all RAM to be be configured
            as data memory.
      2)    The program counter (PC) is set to 0, and the address bus A15-
            A0 is driven with all zeroes while reset is low.
      3)    The data bus D15-D0 is placed in the high impedance state.
      4)    All memory and I/O space control signals are de-asserted by
            setting them to high levels while
            __         __  __  __    _  ____      __
            RC is low (PS, DS, IS, R/W, STRB, and BR).
      5)    All interrupts are disabled by setting the INTM (interrupt
            mode) bit to 1. The interrupt flag register (IFR) is reset to
                                   __
            all zeroes. (Note that RC is non-maskable)
      6)    Status bits:
            0 . OV and 1 . XF (TMS32020); in addition, on the
            TMS320C25, 1 . SXM, 0 . PM, 1 . HM, 0 . FO,
            1 . C, and 1 . FSM. The remaining bits on the TMS320C2x
            are unchanged.
      7)    The global memory allocation register (GREG) is cleared to
            make all memory local.
      8)    The RPTC (repeat counter) is cleared.
      9)    The DX (data transmit) pin is placed in the high-impedance
            state. Any transmit/receive operations on the serial port are
            terminated, and the TXM (transmit mode) bit is reset to a low
            level. This configures the FSX framing pulse to be an input.
            A transmit/receive operation may be started by framing pulses
            only after the removal of the reset signal.
      10)   The TIM register is set to the maximum value (>FFFF) on reset
            for both the TMS32020 and the TMS320C25. The PRD register on
            the TMS320C25 is also initialized by reset to >FFFF. The
            TMS32020 requires a software initialization of the PRD    __
            register. The TIM register begins decrementing only after RS
            is de-asserted.
                ____
      11)   The IACK (interrupt acknowledge) signal is generated in the
            same manner as a maskable interrupt.          __
      12)   The state of the RAM is undefined following a RS.
      13)   The ARB, ARP, DP, IMR, OVM, and TC bits are not initialized
            by reset; therefore it is critical that these bits be
            initialized in software following a reset.
                                                                  __
      Execution starts from location 0 of program memory when the RS
      signal is taken high. Note that if the reset signal is asserted
      while in the hold mode, normal reset occurs internally, but all
      buses and control lines remain in the high-impedance state. Upon
                 ____     __
      release of HOLD and RS, execution starts from location zero. The
      TMS320C2x can be held in the reset state indefinitely.