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      The TMS320C2x contains a 16-bit program counter (PC); it addresses
      program memory, either on-chip or off-chip, via the program address
      bus (PAB). Through the PAB, an instruction is fetched from program
      memory and loaded into the instruction register (IR). When the IR
      is loaded, the PC is ready to start the next instruction fetch
      cycle. The PC may address on-chip RAM block B0 when B0 is configured
      as program memory, or the on-chip ROM provided on the TMS320C25. The
      PC also addresses off-chip program memory through the external
      address bus A15-0 and the external data bus D15-0.

      Data memory is addressed by the program counter during the BLKD
      instruction, which moves data blocks from one section of data memory
      to another. The contents of the accumulator may be loaded into the
      PC in order to implement "computed GOTO" operations. This can be
      accomplished using the BACC (branch to address in accumulator) or
      CALA (call subroutine indirect) instructions.

      To start a new fetch cycle, the PC is loaded either with PC + 1 or
      with a branch address (for instructions such as branches, calls, and
      interrupts). In the case of conditional branches where the branch
      is not taken, the PC is incremented once more beyond the location
      of the branch address.