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      The TMS320C2x has three external maskable interrupts (INT2-INT0),
      available for external devices that interrupt the processor.
      Internal interrupts are generated by the serial port (RINT and
      XINT), by the timer (TINT), and by software interrupt (TRAP)
      instruction. Interrupts are prioritized with reset having the
      highest priority and the serial port transmit interrupt having the
      lowest priority. The TRAP instruction, used for software interrupts,
      is not prioritized but is included in the following table since it
      has its own vector location. Each interrupt address has been spaced
      apart by two locations so that branch instructions can be
      accommodated in those locations if desired.

INTERRUPT OPERATION

      Interrupt    Memory
        Name      Location    Priority          Function
        __
        RS            0       1-highest   External reset signal
        ___
        INT0          2           2       External user interrupt #0
        ___
        INT1          4           3       External user interrupt #1
        ___
        INT2          6           4       External user interrupt #2

        TINT         24           5       Internal timer interrupt
        RINT         26           6       Serial port receive interrupt
        XINT         28           7       Serial port transmit interrupt
        TRAP         30          N/A      TRAP instruction address

      When an interrupt occurs, it is stored in the 6-bit interrupt flag
      register (IFR). This register is set by the external user interrupts
      ___
      INT(2-0) and the internal interrupts RINT, XINT, and TINT. Each
      interrupt is stored in the IFR until it is recognized, and then
                                   ____                            __
      automatically cleared by the IACK (interrupt acknowledge) or RS
      (reset) signals. Reset is not stored in the IFR. No instructions are
      provided for reading from or writing to the IFR.

      The TMS320C2x has a memory-mapped Interrupt Mask Register (IMR) for
      masking internal and external interrupts. A 1 in bit positions 5
      through 0 of the IMR enables the corresponding interrupt, provided
      that INTM = 0. The IMR is accessible with both read and write

       15 14 13 12 11 10  9  8  7  6    5    4    3    2    1    0
      +-----------------------------------------------------------+
      |           reserved          |XINT|RINT|TINT|INT2|INT1|INT0|IMR
      +-----------------------------------------------------------+

      operations, but cannot be read using BLKD. When the IMR is read, the
      unused bits (15 through 6) are read as one's. The lower six bits are
      used to write to or read from the IMR. Reset is not included in the
      IMR, and therefore the IMR has no effect on reset.

      The INTM (interrupt mode) bit, which is bit 9 of status register
      ST0, enables or disables all maskable interrupts. INTM = 0 enables
      all the unmasked interrupts, and INTM = 1 disables these interrupts.

                                ____
      The INTM is set to one by IACK (interrupt acknowledge), the DINT
      instruction, or a reset. This bit is reset to zero by the EINT
      instruction. Note thet the INTM does not actually modify the IMR or
      IFR.

      The TMS320C2x has a built-in mechanism for protecting multi-cycle
      instructions from interrupts. If an interrupt occurs during a multi-
      cycle instruction, the interrupt is not processed until the
      instruction is completed. This mechanism also applies to
      instructions that become multi-cycle due to the READY signal.

      In addition, the device does not allow interrupts to be processed
      when an instruction is being repeated via the RPT or RPTK
      instructions. The interrupt is stored in the IFR until the repeat
      counter (RPTC) decrements to zero, and then the interrupt is
      processed. Even if the interrupt is de-asserted while the TMS320C2x
      is processing the RPT or RPTK, the interrupt will still be latched
      by IFR and pending until the RPTC decrements to zero.
                  ____
      If both the HOLD line and an interrupt go active during a multi-
                                              ____
      cycle instruction or a repeat loop, the HOLD takes control of the
                                                            ____
      processor at the end of the instruction or loop. When HOLD is
      released, the interrupt is acknowledged.

      Interrupts cannot be processed between EINT and the next instruction
      in a program sequence. For example, if an interrupt occurs during
      an EINT instruction execution, the device always completes EINT as
      well as the following instruction before the pending interrupt is
      processed. This ensures that a RET can be executed before the next
      interrupt can be processed, assuming that a RET instruction follows
      the EINT. The state of the machine, upon receiving an interrupt, may
      be saved and restored.