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      The TMS320C2x provides a 16-bit on chip timer and its associated
      interrupt to perform various functions at regular time intervals.
      The timer is a down counter that is continuously clocked by CLKOUT1
      on the TMS320C25, and counts (PRD +1) cycles of CLKOUT1. The timer
      is clocked by CLKOUT1 / 4 on the TMS32020, and counts (4 * PRD)
      cycles of CLKOUT1. By programming the period (PRD) register from 1
      to 65535 (>FFFF), a timer interrupt (TINT) can be generated every
      2 to 65536 cycles on the TMS320C25. Note that a TINT can be
      generated every 4 to 262140 cycles on the TMS32020. A period
      register value of zero is not allowed.

      Two memory-mapped registers are used to operate the timer. The timer
      (TIM) register, data memory location 2, holds the current count of
      the timer. At every CLKOUT1 cycle, the TIM register is decremented
      by one. The PRD register, data memory location 3, holds the starting
      count of the timer. When the TIM register decrements to zero, a
      timer interrupt (TINT) is generated. In the following cycle, the
      contents of the PRD register are loaded into the TIM register. In
      this way, a TINT is generated every (PRD + 1) cycles of CLKOUT1 on
      the TMS320C25 or (4* PRD) cycles of CLKOUT1 on the TMS32020.

      The timer and period registers can be read from or written to on any
      cycle. The count can be monitored by reading the TIM register. A new
      counter period can be written to the PRD register without disturbing
      the current timer count. The timer will then start a new period
      after the current count is complete. If both the PRD and the TIM
      registers are loaded with a new period, the timer begins
      decrementing the new period without generating an interrupt. Thus,
      the programmer has complete control of the current and next periods
      of the timer.

      The TIM register is set to the maximum value on reset (>FFFF) for
      both the TMS32020 and the TMS320C25. The PRD register is also
      initialized by reset on the TMS320C25 to >FFFF. The TMS32020
      requires software initialization of the PRD register. The TIM
      register begins decrementing on after the reset signal is de-
      asserted. If the timer is not used, TINT should be masked. The PRD
      register can then be used as a general-purpose data memory location.
      If TINT is used, the PRD and TIM registers should be programmed
      before unmasking the TINT.

      The following two examples show the assembly code that implements
      the use of the timer to divide down the CLKOUT1 signal. To generate
      a 9600-Hz clock signal, the PRD register should be loaded with 520.
      In the timer interrupt service routine, the XF line is toggled. The
      XF output is also used as an input for BIO in this example. The
      output of XF will provide a 50-percent duty cycle clock signal as
      long as the main routine or other interrupt routines do not disable
      interrupts. Interrupts may be disabled by direct or implied use of
      DINT, or by executing instructions in the repeat mode. The value of
      the PRD register is calculated as follows:

      TMS32020
            CLKOUT1 / (4 * PRD) = 2 * (frequency of signal)
            5 MHz / (4 * 65) = 2 * 9600 (= 9615 Hz for divided signal)

      TMS320C25
            CLKOUT1 / (PRD + 1) = 2 * (frequency of signal)
            10 MHz / (520 + 1) = 2 * 9600 Hz (= 9597 Hz for divided
                                                signal)

EXAMPLE (TMS32020)

*  SETUP FOR INTERRUPT SERVICE ROUTINE.
*
            LACK  65
            SACL  DMA3        ; LOAD THE PERIOD REGISTER
            LACK  8
            OR    DMA4
            SACL  DMA4        ; ENABLE THE TIMER INTERRUPT
            EINT              ; ENABLE INTERRUPTS
            .
            .
            .
*  I/O SERVICE ROUTINE.
*
TIME        BIOZ  SET1        ; CHECK THE CURRENT XF STATE.
            RXF               ; XF WAS HIGH; SET AS LOW.
            EINT              ; ENABLE INTERRUPTS.
            RET               ; RETURN TO INTERRUPTED CODE.
SET1        SXF               ; XF WAS LOW; SET IT HIGH.
            EINT              ; ENABLE INTERRUPTS.
            RET               ; RETURN TO INTERRUPTED CODE.


EXAMPLE (TMS320C25)

*  SETUP FOR INTERRUPT SERVICE ROUTINE.
*
            LACK  520
            SACL  DMA3        ; LOAD THE PERIOD REGISTER
            LACK  8
            OR    DMA4
            SACL  DMA4        ; ENABLE THE TIMER INTERRUPT
            EINT              ; ENABLE INTERRUPTS
            .
            .
            .
*  I/O SERVICE ROUTINE.
*
TIME        BIOZ  SET1        ; CHECK THE CURRENT XF STATE.
            RXF               ; XF WAS HIGH; SET AS LOW.
            EINT              ; ENABLE INTERRUPTS.
            RET               ; RETURN TO INTERRUPTED CODE.
SET1        SXF               ; XF WAS LOW; SET IT HIGH.
            EINT              ; ENABLE INTERRUPTS.
            RET               ; RETURN TO INTERRUPTED CODE.



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