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      Three data processing options allow the ALU to automatically
      suppress sign-extension, manage overflow, or scale product
      accumulations. These options are enabled or disabled through bits
      in the status registers. These options function in parallel with
      normal execution of the instructions and cause no additional machine
      cycles.

      The sign-extension mode option is used to setermine whether or not
      the shifted data values fetched for ALU operations should be sign-
      extended. The SXM status bit controls this operation. This bit is
      set to one for enabling sign-extension using the SSXM instruction,
      and set to zero for suppressing sign-extension using the RSXM
      instruction. This operation affects all the instructions that
      include a shift of the incoming data value, i.e., ADD, ADDT, ADLK,
      LAC, LACT, LALK, SBLK, SFR, SUB, and SUBT.

      The overflow mode option is used to minmize the effects of an
      arithmetic overflow by forcing the accumulator to saturate at the
      largest positive value (or in the case of underflow, the lowest
      possible value). The OVM status bit controls this operation. The
      overflow mode is enabled by setting the OVM bit to one using the
      SOVM instruction, and reset using ROVM instruction. This feature
      affects all arithmetic operations in the ALU.

      The product register shift mode option forces all products to
      shifted before they are accumulated. The products can be left-
      shifted one bit to delete the extra sign bit in the multiply of two
      16-bit signed numbers. The products can be left-shifted four bits
      to delete the extra sign bits in multiplying a 16-bit data value by
      a 13-bit constant. The product shifter can also be used to shift all
      products six bits to the right to allow up to 128 product
      accumulations without the threat of an arithmetic overflow, thereby
      avoiding the overhead of overflow management. The shifter can be
      disabled to cause no shift in the product when working with integer
      or 32-bit precision operations. This also maintains compatibility
      with TMS320C1x code. These operations are controlled by the value
      contained in the PM bits of status register ST1. The PM bits are set
      using the SPM instruction. This feature affects all the instructions
      that use the product of the multiplier, i.e., APAC, LTA, LTD, LTP,
      LTS, MAC, MACD, MPYA, MPYS, PAC, SPAC, SPH, SPL, SQRA, and SQRS.