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SYNTAX      DIRECT   [<LABEL>] TBLW <dma>
            INDIRECT [<LABEL>] TBLW {ind}[,<next ARP>]

OPERANDS    0 . dma . 127; 0 . next ARP . 7.

EXECUTION   TMS32020
                  (PC) + 1 . TOS
                  (ACC(15-0)) . PC
                  If (repeat counter) is not equal to zero:
                        Then (dma) . pma,
                             modify AR(ARP) and ARP as specified,
                             (PC) + 1 . PC,
                             (repeat counter) - 1 . repeat counter;
                        Else (dma) . pma,
                             modify AR(ARP) and ARP as specified.
                  (TOS) . PC

             TMS320C25
                  (PC) + 1 . PC
                  (PFC) . MCS
                  (ACC(15-0)) . PFC
                  If (repeat counter) is not equal to zero:
                        Then (dma, addressed by the PFC) . pma,
                             modify AR(ARP) and ARP as specified,
                             (PFC) + 1 . PFC,
                             (repeat counter) - 1 . repeat counter;
                        Else (dma, addressed by PFC) . pma,
                             modify AR(ARP) and ARP as specified.
                  (MCS) . PFC

DESCRIPTION The TBLW instruction transfers a word in data memory to
            program memory. The data memory address is specified by the
            instruction, and the program memory address is specified by
            the lower 12 bits of the accumulator. A read from data memory
            is followed by a write to program memory to complete the
            instruction. When in the repeat mode, TBLW effectively becomes
            a single-cycle instruction, and the program counter that
            contains the ACCL is incremented once each cycle. On the
            TMS32020, the contents of the lowest stack location are lost
            when using the TBLW instruction.
                      __
            If the MP/MC pin on the TMS320C25 is low at the time of
            execution of this instruction and the program memory address
            used is lower than 4096, an on-chip ROM location will be
            addressed but not written.

WORDS       1

ENCODING    15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |0  1  0  1  1  0  0  1| 0|data memory address 2| DIRECT
            +-----------------------------------------------+

            15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |0  1  0  1  1  0  0  1| 1| see indirect fields | INDIRECT
            +-----------------------------------------------+


CYCLES

         +----------------------------------------------------------+
         |           Cycle Timings for a Single Instruction         |
         |----------------------------------------------------------|
         | PI/DI |   PI/DE  |  PE/DI |    PE/DE   | PR/DI|  PR/DE   |
         |----------------------------------------------------------|
      '20|             Table in internal program memory             |
         |----------------------------------------------------------|
         |   3   |    3+d   |   3+p  |    3+d+p   |   -  |    -     |
         |----------------------------------------------------------|
      '20|             Table in external program memory             |
         |----------------------------------------------------------|
         |  3+p  |   4+d+p  |  3+2p  |   4+d+2p   |   -  |    -     |
         |----------------------------------------------------------|
     'C25|                  Table in on-chip RAM                    |
         |----------------------------------------------------------|
         |   2   |    3+d   |   3+p  |    4+d+p   |   3  |   4+d    |
         |----------------------------------------------------------|
     'C25|                  Table in on-chip ROM                    |
         |----------------------------------------------------------|
         |                     not applicable                       |
         |----------------------------------------------------------|
     'C25|                Table in external memory                  |
         |----------------------------------------------------------|
         |  2+p  |  3+d+p   |  3+2p  |   4+d+2p   |  3+p |  4+d+p   |
         |----------------------------------------------------------|
         |          Cycle Timings for a Repeat Instruction          |
         |----------------------------------------------------------|
         | PI/DI |   PI/DE  |  PE/DI |    PE/DE   | PR/DI|  PR/DE   |
         |----------------------------------------------------------|
      '20|              Table in internal program memory            |
         |----------------------------------------------------------|
         |  2+n  |  2+n+nd  |  2+n+p |  2+n+nd+p  |   -  |    -     |
         |----------------------------------------------------------|
      '20|              Table in external program memory            |
         |----------------------------------------------------------|
         |2+n+np |2+2n+nd+np|2+n+np+p|2+2n+nd+np+p|   -  |    -     |
         |----------------------------------------------------------|
     'C25|                  Table in on-chip RAM                    |
         |----------------------------------------------------------|
         |  1+n  |  2+n+nd  |  2+n+p |  3+n+nd+p  |  2+n |  3+n+nd  |
         |----------------------------------------------------------|
     'C25|                  Table in on-chip ROM                    |
         |----------------------------------------------------------|
         |                     not applicable                       |
         |----------------------------------------------------------|
     'C25|                Table in external memory                  |
         |----------------------------------------------------------|
         | 1+n+np|1+2n+nd+np|2+n+np+p|2+2n+nd+np+p|2+n+np|2+2n+nd+np|
         +----------------------------------------------------------+



EXAMPLE     TBLW  DAT5        (DP = 32)
            or
            TBLW  *           If current auxiliary register contains 4101.

                BEFORE             AFTER

               ACC  >257         ACC  >257
            dm4101 >4339      dm4101 >4339
             pm257  >306       pm257 >4339