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SYNTAX DIRECT [<LABEL>] LT <dma>
INDIRECT [<LABEL>] LT {ind}[,<next ARP>]
OPERANDS 0 . dma . 127; 0 . next ARP . 7.
EXECUTION (PC) + 1 . PC
(dma) . T register
DESCRIPTION The T register is loaded with the contents of the specified
data memory address (dma). The LT instruction may be used to
load the T register in preparation for multiplication. See the
LTA, LTD, LTP, LTS, MPY, MPYK, MPYA, MPYS, and MPYU
instructions.
WORDS 1
ENCODING 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+-----------------------------------------------+
|0 0 1 1 1 1 0 0| 0| data memory address | DIRECT
+-----------------------------------------------+
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+-----------------------------------------------+
|0 0 1 1 1 1 0 0| 1| see indirect fields | INDIRECT
+-----------------------------------------------+
CYCLES
+------------------------------------------------+
| Cycle Timings for a Single Instruction |
|------------------------------------------------|
| PI/DI | PI/DE | PE/DI | PE/DE | PR/DI | PR/DE |
|-------+-------+-------+--------+-------+-------|
'20 | 1 | 2+d | 1+p | 2+d+p | - | - |
|-------+-------+-------+--------+-------+-------|
'C25 | 1 | 2+d | 1+p | 2+d+p | 1 | 2+d |
|------------------------------------------------|
| Cycle Timings for a Repeat Instruction |
|------------------------------------------------|
'20 | n | 2n+nd | n+p | 2n+nd+p| - | - |
|-------+-------+-------+--------+-------+-------|
'C25 | n | 1+n+nd| n+p |1+n+nd+p| n |1+n+nd |
+------------------------------------------------+
EXAMPLE LT DAT24 (DP = 8)
or
LT * If current auxiliary register contains 1048.
BEFORE AFTER
dm1048 >62 dm1048 >62
T >3 T >62