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SYNTAX      DIRECT   [<LABEL>] LAR <AR>,<dma>
            INDIRECT [<LABEL>] LAR <AR>,{ind}[,<next ARP>]

OPERANDS    0 . dma . 127; 0 . auxiliary register AR . 7;
            0 . next ARP . 7.

EXECUTION   (PC) + 1 . PC
            (dma) . auxiliary register AR

DESCRIPTION The contents of the specified data memory address are loaded
            into the designated auxiliary register (AR).

            The LAR and SAR (store auxiliary register) instructions can
            be used to load and store the auxiliary registers during
            subroutine calls and interrupts. If an auxiliary register is
            not being used for indirect addressing, LAR and SAR enable the
            register to be used as an additional storage register,
            especially for swapping values between data memory locations
            without affecting the contents of the accumulator.

WORDS       1

ENCODING    15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |0  0  1  1  0|   AR   | 0| data memory address | DIRECT
            +-----------------------------------------------+

            15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |0  0  1  1  0|   AR   | 1| see indirect fields | INDIRECT
            +-----------------------------------------------+

CYCLES

            +------------------------------------------------+
            |    Cycle Timings for a Single Instruction      |
            |------------------------------------------------|
            | PI/DI | PI/DE | PE/DI | PE/DE  | PR/DI | PR/DE |
            |-------+-------+-------+--------+-------+-------|
      '20   |   1   |  2+d  |  1+p  | 2+d+p  |   -   |   -   |
            |-------+-------+-------+--------+-------+-------|
     'C25   |   1   |  2+d  |  1+p  | 2+d+p  |   1   |  2+d  |
            |------------------------------------------------|
            |    Cycle Timings for a Repeat Instruction      |
            |------------------------------------------------|
      '20   |   n   | 2n+nd |  n+p  |2n+nd+p |   -   |   -   |
            |-------+-------+-------+--------+-------+-------|
     'C25   |   n   | 2n+nd |  n+p  |2n+nd+p |   n   | 2n+nd |
            +------------------------------------------------+



EXAMPLE     LAR   AR0,DAT10   (DP = 4)

               BEFORE             AFTER

            dm522 >18         dm522 >18
              AR0  >6           AR0 >18

EXAMPLE     LARP  AR4
            LAR   AR4,*-

                BEFORE             AFTER

            dm617  >32         dm617 >32
              AR4 >617           AR4 >32

            Note LAR, in the indirect addressing mode, ignores any AR
            modifications if the AR specified by the instruction is the
            same as that pointed to by the ARP. Therefore, in the latter
            example, AR4 is not decremented after the LAR instruction.