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The auxiliary registers (AR) provide flexible and powerful indirect
addressing. Five auxiliary registers (AR0-AR4) are provided on the
TMS32020, and eight auxiliary registers (AR0-AR7) are available on the
TMS320C25. To select a specific auxiliary register, the Auxiliary Register
Pointer (ARP) is loaded with a value of 0 through 4 or 7, designating AR0
through AR4 or AR7, respectively.

The contents of the auxiliary registers may be operated upon by the
Auxiliary Register Arithmetic Unit (ARAU), which implements 16-bit
unsigned arithmetic. The ARAU performs auxiliary register arithmetic
operations in the same cycle as the execution of the instruction. Note
that the increment or decrement of the indicated AR is always executed
after the use of that AR in the instruction.

In indirect addressing, any location in the 64K data memory space can be
accessed via the 16-bit addresses contained in the auxiliary registers.
These may be loaded by the instructions LAR (load auxiliary register),
LARK (load auxiliary register immediate), and LRLK (load auxiliary
register long immediate). The auxiliary registers on the TMS320C25 may be
modified by ADRK (add to auxiliary register short immediate) or SBRK
(subtract from auxiliary register short immediate). The TMS320C2x
auxiliary registers may also be modified by the MAR (modify auxiliary
register) instruction or, equivalently, by the indirect addressing field
of any instruction supporting indirect addressing. AR(ARP) denotes the
auxiliary register selected by ARP.

The following symbols are used in indirect addressing, including bit-
reversed (BR) addressing:

      *     Contents of AR(ARP) are used as the data memory address.
      *-    Contents of AR(ARP) are used as the data memory address, then
            decremented after the access.
      *+    Contents of AR(ARP) are used as the data memory address, then
            incremented after the access.
      *0-   Contents of AR(ARP) are used as the data memory address, and
            the contents of AR0 subtracted from it after the access.
      *0+   Contents of AR(ARP) are used as the data memory address, and
            the contents of AR0 added to it after the access.
      *BR0- Contents of AR(ARP) are used as the data memory address, and
            the contents of AR0 subtracted from it, with reverse carry
            (rc) propagation, after the access (TMS320C25 specific).
      *BR0+ Contents of AR(ARP) are used as the data memory address, and
            the contents of AR0 added to it, with reverse carry (rc)
            propagation, after the access (TMS320C25 specific).

There are two main types of indirect addressing with indexing:

      Regular indirect addressing with increment or decrement, and

      Indirect addressing with indexing based on the value of AR0:
            Indexing by adding or subtracting the contents of AR0, or
            Indexing by adding or subtracting the contents of AR0 with the
            carry propagation reversed (for FFT's on the TMS320C25).

In either case, the contents of the auxiliary register pointed to by the
ARP register are used as the address of the data memory operand. Then, the
ARAU performs the specified mathematical operation on the indicated
auxiliary register. Additionally, the ARP may be loaded with a new value.
All indexing operations are performed on the current auxiliary register
in the same cycle as the original instruction.

Indirect auxiliary register addressing allows for post-access adjustments
of the auxiliary register pointed to by the ARP. The adjustment may be an
increment or decrement by one based upon the contents of AR0.

Bit-reversed addressing modes on the TMS320C25 allow efficient I/O to be
performed for the resequencing of data points in the radix-2 FFT program.
The direction of carry propagation in the ARAU is reversed when this mode
is selected and AR0 is added to/subtracted from the current auxiliary
register. Typical use of this addressing mode requires that AR0 first be
set to a value corresponding to one-half the array size, and AR(ARP) be
set to the base address of the data (the first data point). See also FFT
for use of bit-reversed addressing modes.

Indirect addressing can be used with all instructions except immediate
operand instructions and those with no operands. The indirect addressing
format is as follows:

       15 14 13 12 11 10  9  8  7   6   5   4   3  2  1  0
       +---------------------------------------------------+
       |         opcode       | 1|IDV|INC|DEC|NAR|    Y    | INDIRECT
       +---------------------------------------------------+

Bits 15 through 8 contain the opcode, and bit 7 = 1 defines the addressing
mode as indirect. Bits 6 through 0 contain the indirect addressing control
bits.

Bit 6 contains the increment/decrement value IDV. The IDV determines
whether AR0 will be used to increment or decrement the current auxiliary
register. If bit 6 = 0, then an increment or decrement (if any)  by one
occurs to the current auxiliary register. If bit 6 = 1, then AR0 may be
added or subtracted from the current auxiliary register as defined by bits
5 and 4.

Bits 5 and 4 control the aritmetic operation to be performed with AR(ARP)
and AR0. When set, bit 5 indicates that an increment is to be performed.
If bit 4 is set, a decrement is to be performed.

Bit 3 and bits 2 through 0 control the Auxiliary Register Pointer (ARP).
Bit 3 (NAR) determines if a new value is loaded into the ARP. If bit 3 =
1, the contents of bit s 2 through 0 (Y = next ARP) are loaded into the
ARP. If bit 3 = 0, the contents of the ARP remain unchanged.

                    Indirect Addressing Operations

              Bits        Notation        Arithmetic Operation
 15-8  7  6  5  4  3  2-0
opcode 1  0  0  0  0   Y  *        No manipulation of ARs/ARP
opcode 1  0  0  0  1   Y  *,Y      Y . ARP
opcode 1  0  0  1  0   Y  *-       AR(ARP) - 1 . AR(ARP)
opcode 1  0  0  1  1   Y  *-,Y     AR(ARP) - 1 . AR(ARP), Y . ARP
opcode 1  0  1  0  0   Y  *+       AR(ARP) + 1 . AR(ARP)
opcode 1  0  1  0  1   Y  *+,Y     AR(ARP) + 1 . AR(ARP), Y . ARP
          0  1  1                  Reserved
opcode 1  1  0  0  0   Y  *BR0-    AR(ARP) - rcAR0 . AR(ARP) [BR = bit
                                   reversed, rc = reverse carry, 'C25]
opcode 1  1  0  0  1   Y  *BR0-,Y  AR(ARP) - rcAR0 . AR(ARP) [BR = bit
                                   reversed, rc = reverse carry, 'C25],
                                   Y . ARP
opcode 1  1  0  1  0   Y  *0-      AR(ARP) - AR0 . AR(ARP)
opcode 1  1  0  1  1   Y  *0-,Y    AR(ARP) - AR0 . AR(ARP), Y . ARP
opcode 1  1  1  0  0   Y  *0+      AR(ARP) + AR0 . AR(ARP)
opcode 1  1  1  0  1   Y  *0+,Y    AR(ARP) + AR0 . AR(ARP), Y . ARP
opcode 1  1  1  1  0   Y  *BR0+    AR(ARP) + rcAR0 . AR(ARP) [BR = bit
                                   reversed, rc = reverse carry]
opcode 1  1  1  1  1   Y  *BR0+,Y  AR(ARP) + rcAR0 . AR(ARP) [BR = bit
                                   reversed, rc = reverse carry, 'C25],
                                   Y . ARP

For some instructions, the preceding table notation includes a shift code,
e.g., *0+,8,3 where 8 is the shift code and Y = 3.

The CMPR (compare auxiliary register with AR0) and BBZ/BBNZ (branch if TC
bit equal/not equal to zero) instructions facilitate conditional branches
based on comparisons between the contents of AR0 and the contents of
AR(ARP).

The auxiliary registers may also be used for temporary storage via the
load and store auxiliary register instructions, LAR and SAR, respectively.

Example 1 of Indirect Addressing Format:

      ADD   *+,8        Add to the accumulator the contents of data memory
                        address defined by the contents of the current
                        auxiliary register. This data is shifted 8 bits
                        before being added. The current auxiliary register
                        is auto-incremented by one. The opcode is >08A0:

        15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
        +-----------------------------------------------+
        |0  0  0  0  1  0  0  0| 1| 0  1  0  0  0  0  0 | INDIRECT
        +-----------------------------------------------+

Ex.2  ADD   *,8         As in example 1, but with no auto-increment, the
                        opcode is >0880.
Ex.3  ADD   *-,8        As in example 1, except that the current auxiliary
                        register is decremented by one; the opcode is
                        >0890.
Ex.4  ADD   *0+,8       As in example 1, except that the contents of
                        auxiliary register AR0 are added to the current
                        auxiliary register; the opcode is >08E0.
Ex.5  ADD   *0-,8       As in example 1, except that the contents of
                        auxiliary register AR0 are subtracted from the
                        current auxiliary register; the opcode is >08D0.
Ex.6  ADD   *+,8,3      As in example 1, except that the auxiliary
                        register pointer (ARP) is loaded with the value
                        of 3 for subsequent instructions; the opcode is
                        >08AB.
Ex.7  ADD   *BR0-,8     The opcode is >08C0. The contents of auxiliary
                        register AR0 are subtracted from the current
                        auxiliary register with reverse carry propagation
                        (TMS320C25).
Ex.8  ADD   *BR0+,8     The opcode is >08F0. The contents of auxiliary
                        register AR0 are added to the current auxiliary
                        register with reverse carry propagation
                        (TMS320C25).