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SYNTAX      [<LABEL>] EINT

OPERANDS    None

EXECUTION   (PC) + 1 . PC
            0 . interrupt mode (INTM) status bit
            Affects INTM.

DESCRIPTION The interrupt- mode flag (INTM) in the status register is
            cleared to logic 0.  Maskable interrupts are enabled after the
            instruction following EINT executes.  This allows an interrupt
            service routine to re-enable interrupts and execute a RET
            instruction before any other pending interrupts are processed.

            Note that the LST instruction does not affect INTM.  (See the
            DINT instruction for further information).

WORDS       1

ENCODING    15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
            +-----------------------------------------------+
            |1  1  0  0  1  1  1  0  0  0  0  0  0  0  0  0 |
            +-----------------------------------------------+

CYCLES

            +------------------------------------------------+
            |    Cycle Timings for a Single Instruction      |
            |------------------------------------------------|
            | PI/DI | PI/DE | PE/DI | PE/DE  | PR/DI | PR/DE |
            |-------+-------+-------+--------+-------+-------|
      '20   |   1   |   1   |  1+p  |  1+p   |   -   |   -   |
            |-------+-------+-------+--------+-------+-------|
     'C25   |   1   |   1   |  1+p  |  1+p   |   1   |   1   |
            |------------------------------------------------|
            |    Cycle Timings for a Repeat Instruction      |
            |------------------------------------------------|
      '20   |   n   |   n   |  n+p  |  n+p   |   -   |   -   |
            |-------+-------+-------+--------+-------+-------|
     'C25   |   n   |   n   |  n+p  |  n+p   |   n   |   n   |
            +------------------------------------------------+



EXAMPLE     EINT        Maskable interrupts are disabled, and INTM is set
                        to zero.