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  The microprocessor responds to a hardware interrupt in much the same way
  it responds to a software interrupt: by transferring control to an
  interrupt handler. The important difference lies in the way the interrupt
  is signalled.

  Devices such as the system timer, the hard disk, the keyboard, and the
  serial communications ports can generate interrupt signals on a set of
  reserved interrupt request (IRQ) lines. These lines are monitored by the
  PIC circuit, which assigns interrupt numbers to them. When a particular
  hardware interrupt occurs, the PIC places the corresponding interrupt
  number on the system data bus where the microprocessor can find it.

  The PIC also assigns priorities to the various interrupt requests. For
  example, the highest-priority PIC interrupt in all PCs and PS/2s is the
  timer-tick interrupt, which is signalled on interrupt request line 0
  (IRQ0) and is assigned interrupt 08H by the PIC. When a system timer
  generates a timer- tick interrupt, it does so by signalling on IRQ0; the
  PIC responds by signalling the CPU to execute interrupt 08H. If a
  lower-priority hardware interrupt request occurs while the timer-tick
  interrupt is being processed, the PIC delays the lower-priority interrupt
  until the timer interrupt handler signals that it has finished its
  processing.

  When you coldboot the computer, the system start-up routines assign
  interrupt numbers and priorities to the hardware interrupts by
  initializing the PIC. In 8088- and 8086-based machines (PCs, PC/XTs, PS/2
  models 25 and 30), interrupt numbers 08H through 0FH are assigned to
  interrupt request levels 0 through 7 (IRQ0 through IRQ7). In PC/ATs and
  PS/2 models 50, 60, and 80, an additional eight interrupt lines (IRQ8
  through IRQ15) are assigned interrupt numbers 70H through 77H.

  One hardware interrupt bypasses the PIC altogether. This is the
  non-maskable interrupt (NMI), which is assigned interrupt number 02H in
  the 8086 family. The NMI is used by devices that require absolute,
  "now-or-never" priority over all other CPU functions. In particular, when
  a hardware memory error occurs, the computer's RAM subsystem generates an
  NMI. This causes the CPU to pass control to an interrupt 02H handler; the
  default handler in the PC family resides in ROM and issues the "PARITY
  CHECK" message you see when a memory error occurs.

  When you debug a program on any member of the PC family, remember that
  hardware interrupts are occurring all the time. For example, the system
  timer-tick interrupt (interrupt 08H) occurs roughly 18.2 times per second.
  The keyboard and disk-drive controllers also generate interrupts. Each
  time these hardware interrupts occur, the 8086 uses the current stack to
  save CS:IP and the flags register. If your stack is too small, or if you
  are manipulating SS and SP when a hardware interrupt occurs, the 8086 may
  damage valuable data when it saves CS:IP and the flags.

  If you look back at our example of updating SS and SP on page 36, you'll
  see that we explicitly disable hardware interrupts by executing the CLI
  instruction prior to updating SS. This prevents a hardware interrupt from
  occurring between the two MOV instructions while SS:SP is pointing
  nowhere. (Actually, this is a problem only in very early releases of the
  8088; the chip was later redesigned to prevent this problem by disabling
  interrupts during the instruction that follows a data move into SS.)

  We'll talk in more detail about how PCs and PS/2s use interrupts in
  Chapters 3 and 8.