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SAR              Shift Arithmetic Right              Flags: O D I T S Z A P C
                                                            *       * * ? * *
SAR destination,count

                    +----+   +-------------+   +----+
                    | SF |--.| Destination |--.| CF |
                    +----+   +-------------+   +----+

    SAR shifts the word or byte in destination to the right by the number
    of bit positions specified in the second operand, COUNT. As bits are
    transferred out the right (low-order) end of the destination, bits
    equal to the original sign bit are shifted into the left (high-order)
    end, thereby preserving the sign bit. The Carry Flag is set equal to
    the last bit shifted out of the right end.

    If COUNT is not equal to 1, the Overflow flag is undefined. If COUNT
    is equal to 1, the Overflow flag is cleared.

  --------------------------------------------------------------------------
   Operands                  Clocks   Transfers  Bytes   Example
                           byte(word)
   register, 1                 2          -        2     SAR DX,1
   register, CL            8 + 4/bit      -        2     SAR DI,CL
   memory, 1              15(23) + EA     2       2-4    SAR N_BLOCKS,1
   memory, CL           20(28)+EA+4/bit   2       2-4    SAR N_BLOCKS,CL
  --------------------------------------------------------------------------

       Notes:         COUNT is normally taken as the value in CL. If,
                      however, you wish to shift only one position,
                      replace the second operand, CL, with the value 1, as
                      shown in the first example above.

                      The 80286 and 80386 microprocessors limit the COUNT
                      value to 31.  If the COUNT is greater than 31, these
                      microprocessors use COUNT MOD 32 to produce a new
                      COUNT between 0 and 31.  This upper bound exists to
                      limit the amount of time an interrupt response will
                      be delayed waiting for the instruction to complete.

                      Multiple SARs that use 1 as the COUNT may be faster
                      and require less memory than a single SAR that uses
                      CL for COUNT.

                      The overflow flag is undefined when the shift count
                      is greater than 1.