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          Creating a split screen

          the VGA hardware supports a split screen. The top portion
          of the screen is designated as screen A, and the button
          portion is designated as screen B, as in the figure below:

                           +------------------------+
                           |                        |
                           |        Screen A        |
                           |                        |
                           |------------------------|
                           |                        |
                           |        Screen B        |
                           |                        |
                           +------------------------+

          The following figure shows the screen mapping for a system
          containing a 32Kb alphanumeric storage buffer, such as the
          VGA.

          Information displayed on screen A is defined by the Start
          Address High and Low register on the CRT controller.
          Information displayed on screen B always begins at video
          address 0000h.

          0000h  +--------------------------+
                 |         Screen B         |
                 |                          |
          0FFFh  |   Buffer storage area    |
                 |--------------------------|
          1000h  |         Screen A         |
                 |                          |
                 |   Buffer storage area    |
          7FFFh  +--------------------------+

          The Line Compare register of the CRT controller performs
          the spilt screen function. The CRT controller has an
          internal horizontal scan line counter and logic that
          compares the counter value to the value in the Line compare
          register and clears the memory address generator when a
          comparison occurs. The linear address generator then
          sequentially addresses the display buffer starting at
          location 0. Each subsequent row address is determined by
          the 16-bit addition of the start-of line latch and the
          Offset register.

          Screen B can be smoothly scrolled onto the display by
          updating the line compare register with the vertical
          retrace signal. Screen B information is not affected by
          scrolling operations that use the Start Address register to
          scroll through the screen A information.

          When PEL-panning compatibility is enables (Attribute Mode
          Control register), a successful line comparison forces the
          output of the Horizontal Panning register to 0's until a
          vertical synchronization occurs. This feature allows the
          information on screen B to remain unaffected by PEL-panning
          operations on screen A.