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         VGA Programming Considerations

         The following are some programming considerations for the VGA:

         .  The following rules must be followed to guarantee the
            critical timings necessary to ensure proper operation of the
            CRT controller:

            -  The value in the Horizontal Total register must be at
               lease 19h.
            -  The minimum positive pulse width of the 'horizontal
               synchronization' signal must be four character clock
               units.
            -  The End Horizontal Retrace register must be programmed
               such that the 'horizontal synchronization' signal goes to
               0 at least one character before the 'horizontal display
               enable' signal goes active.
            -  The End Vertical Blanking register must be set to a
               minimum of one horizontal scan line greater than the line-
               compare value.

         .  When PEL panning compatibility is enabled in the Attribute
            Mode Control Register, a successful line compare in the CRT
            controller forces the output of the Horizontal PEL Panning
            register to 0's until a vertical synchronization occurs. When
            the vertical synchronization occurs, the output returns to
            the programmed value. This allows the portion of the screen
            indicated by the Line Compare Register to be operated on by
            the Horizontal PEL Panning Register.

         .  A write to the Character Map Select register becomes valid on
            the next whole character line. This will prevent deformed
            character images when changing character generators in the
            middle of a scan line.

         .  For mode 13h, the attribute controller is configured so that
            the 8-bit attribute in the video memory becomes the 8-bit
            address (P0-P7) into the video DAC. The user should not
            modify the contents of the Internal Palette Registers when
            using this mode.

         .  The following is the sequence for accessing the attribute
            data registers:

            1. Disable interrupts.
            2. Reset the flip-flop for the Attribute Address register.
            3. Write the index
            4. Access the data register.
            5. Enable interrupts.

         .  The Color Select register in the attribute controller section
            allows the programmer to rapidly switch color sets in the
            video DAC. Bit 7 of the Attribute Mode Control register
            controls the number of bits in the Color Select register used
            to address the color information in the video DAC (either two
            or four bits are used). By changing the value in the Color
            Select register, an application can switch color sets in
            graphics and alphanumeric modes (mode 13h does not use the
            feature).

            Note: For multiple color sets, the user must load the color
                  values.

         .  An application that saves the video state must store the four
            bytes of information contained in the system microprocessor
            latches in the graphics controller subsection. These latches
            are loaded with 32 bits from video memory (8 bits per map)
            each time the system reads from video memory. The application
            needs to:

            1. Use write mode 1 to write the values in the latches to a
               location in video memory that is not part of the display
               buffer, such as the last location in the address range.
            2. Save the values of the latches by reading them back from
               video memory.

               Note: If memory addressing is in the chain-4 or odd/even
                     mode, reconfigure the memory as four sequential maps
                     prior to performing the sequence above.

            BIOS provides support for completely saving and restoring the
            video state.

         .  The Horizontal PEL Panning register controls the number of
            PELs shifted left. Further panning, beyond that shown under
            the register control, can be accomplished by changing the
            start-address value in the CRT controller registers, Start
            Address High and Start Address Low. The sequence is:

            1. Use the Horizontal PEL Panning register to shift the
               maximum number of bits to the left.
            2. Increment the start address.
            3. Set the Horizontal PEL Panning register so that no bits
               are shifted.

               The screen will now be shifted one PEL to the left of the
               position it was in at the end of step 1. Step 1 through 3
               are repeated as often as necessary.

         .  When using a split-screen application that scroll a second
            screen on top of the first screen and operating in a mode
            with 200 scan lines, the Line Compare register (CRT
            controller register 19h) must contain an even value. This is
            a requirement of the double scanning logic in the CRT
            controller.

         .  If the value in the Cursor Start register (CRT Controller
            register 0Ah) is greater than that in the Cursor End Register
            (CRT controller 0Bh), the cursor is not displayed.

         .  In 8-dot character modes, the underline attribute produces a
            solid line across adjacent character. In 9-dot character
            modes the underline across adjacent characters is dashed. In
            9-dot modes with the line-graphics characters (C0h-DFh
            character codes), the underline is solid.