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        Abbreviations and legends

        ST   ST(0)
        reg  floating point data register
        mem  memory address
        m16  memory address of 16-bit item
        m32  memory address of 32-bit item
        m64  memory address of 64-bit item
        m80  memory address of 80-bit item
        **   to the power of, e.g. 2**X = 2 to the Xth power


        Exceptions
        S   invalid operand due to stack overflow/underflow (387+)
        I   invalid operand due to other cause
        D   denormal operand
        Z   zero-divide
        O   overflow
        U   underflow
        P   inexact result (precision)


        Condition codes
        *   changed to reflect the results of instruction
        ?   undefined after operation (may or may not have changed)
        0   always cleared


        FPU instruction timings
        EA  cycles to calculate the Effective Address
        FX  pairs with FXCH  (Pentium)
        NP  not pairable     (Pentium)

        Timings with a hyphen indicate a range of possible timings.
        Timings with a slash (unless otherwise noted) are latency
          and throughput.
        Latency is the time between instructions dependent on the result.
        Throughput is the pipeline throughput between non conflicting
          instructions.


        FPU instruction length
        All FPU instructions that do not access memory are two bytes
        in length, except FWAIT which is one byte; 'wait' versions
        are are one byte longer as an FWAIT is inserted before the
        instruction.

        FPU instructions that access memory are four bytes for 16-bit
        addressing and six bytes for 32-bit addressing.