Click above to get retro games delivered to your door ever month!

SHL              Shift Logical Left                  Flags: O D I T S Z A P C
                                                            *       * * ? * *
SHL destination,count

                       +----+   +-------------+
                       | CF |.--| Destination |.-- 0
                       +----+   +-------------+

    SHL is the same instruction as SAL, Shift Arithmetic Left. SHL shifts
    the word or byte at the destination to the left by the number of bit
    positions specified in the second operand, COUNT. As bits are
    transferred out the left (high-order) end of the destination, zeroes
    are shifted in the right (low-order) end. The Carry Flag is updated to
    match the last bit shifted out of the left end.

    If COUNT is not equal to 1, the Overflow flag is undefined. If COUNT
    is equal to 1, the Overflow Flag is cleared if the top 2 bits of the
    original operand were the same, otherwise the Overflow Flag is set.

  --------------------------------------------------------------------------
   Operands                  Clocks   Transfers  Bytes   Example
                           byte(word)
   register, 1                 2          -        2     SHL AL,1
   register, CL            8 + 4/bit      -        2     SHL SI,CL
   memory, 1              15(23) + EA     2       2-4    SHL WORD,1
   memory, CL           20(28)+EA+4/bit   2       2-4    SHL BYTE,CL
  --------------------------------------------------------------------------

       Notes:         COUNT is normally taken as the value in CL. If,
                      however, you wish to shift only one position,
                      replace the second operand, CL, with the value 1, as
                      shown in the first example below.

                      The 80286 and 80386 microprocessors limit the COUNT
                      value to 31.  If the COUNT is greater than 31, these
                      microprocessors use COUNT MOD 32 to produce a new
                      COUNT between 0 and 31.  This upper bound exists to
                      limit the amount of time an interrupt response will
                      be delayed waiting for the instruction to complete.

                      Multiple SHLs that use 1 as the COUNT may be faster
                      and require less memory than a single SHL that uses
                      CL for COUNT.

                      The overflow flag is undefined when the shift count
                      is greater than 1.